Micron demonstrates 232 layer NAND package with 2TB storage

29-07-2022 |   |  By Robin Mitchell

Recently, Micron announced the release of the world’s first 232-layer NAND chip that offers 1Tb per die and 2TB per package. What challenges do semiconductor technologies face when increasing in size, what does the new NAND chip offer, and how does this demonstrate the power of going vertical?

What challenges do semiconductors face when increasing in size?

Ever since the first integrated circuits, researchers have continuously looked for technologies that can reduce the size of individual transistors. Smaller transistors equate to increased transistor density which can either be used to reduce the size of the resulting chip or increase the number of transistors on that chip. Additionally, reducing the size of transistors also decreases the voltage they operate at and lowers the current they consume, resulting in less energy consumed. As such, small transistors have been the key to both high-performance CPUs in supercomputers and low-energy mobile processors.

But unfortunately, transistor sizes are quickly approaching physical limits, which will eventually see an absolute minimum size. Many thought that going below 10nm would be impossible, but alas, researchers found ways to make it possible, and we are now seeing transistors with 3nm features. Even then, there will be a time when transistors using traditional materials cannot be reduced in size.

However, instead of going smaller, many foundries have been exploring the vertical space to increase transistor densities. Most semiconductors are planar devices meaning that all active components sit on a single layer on a die. Considering that a chip is generally no more than 2mm thick, there is plenty of vertical room to increase the number of transistors on a chip. For example, adding a second die automatically doubles the number of transistors in the overall package.

But there are challenges with going upwards instead of outwards. One such challenge is heat dissipation from either die, as stacking two dies on top of each other increases thermal resistance (i.e. the ease of removing heat). Another challenge is finding technologies that can align dies and connect them together. It is trivial to connect two dies together that have 16 connections between them (resulting in large contact pads), but two halves of a processor would have thousands, and these would need to be perfectly aligned. 

Micron releases the world’s first 232-layer NAND flash memory

Demonstrating the power of going vertical, Micron has recently announced the release of their latest memory NAND chip that uses a total of 232 active layers. NAND memory is one of the few technologies that can currently be made vertical (due to the nature of NAND circuitry using series transistors), and most NAND flash manufacturers now produce 3D designs. But the chip developed by Micron is the world’s first 232 layer offering new memory densities currently unseen in solid-state offerings.

The new die developed by Micron has a total storage capacity of 1Tb (terabit) that also has the industry’s highest access speed of 2.4GB per second. Additionally, the new technology also offers a 100% increase in write bandwidth and 75% higher read bandwidth per die compared to previous Micron NAND chip generations. However, Micron has taken their die further by combining multiple dies to create a 2TB (terabyte) package with a dimension of 11.5mm x 13.5mm. This represents a size reduction of 28%, which helps designs increase their memory capacity while reducing the overall size.

How does the new NAND flash chip demonstrate the power of going vertical?

As improvements in NAND flash are made, the number of layers continues to increase, which increases memory density, and yet, the height of such packages is marginal at most. This means that a chip with the same height as previous generations can increase the amount of data stored without impacting its physical size or weight. Of course, a future NAND chip with ten thousand layers would quickly become thick, but the storage capability at such layer counts would be in the petabytes of storage.

Fundamentally, this new NAND chip demonstrates that going vertical on a semiconductor can quickly increase transistor density without physically shrinking the size of individual transistors. While 3D NAND technologies are not the same as planar technologies used to create transistors, a 3D silicon die that can integrate transistors on multiple layers would present engineers with immense possibilities.

For example, modern processors (such as the Apple M1) are taking advantage of parallel computing and using simpler RISC cores instead of complex CISC cores. Even though RISC cores are physically smaller than CISC cores, only so many can fit on a planar device. As such, stacking multiple RISC dies could quickly increase the number of cores without needing to shrink transistors.

Another significant advantage of die stacking is improvements in semiconductor yield. Crystalline wafers used to create semiconductors (such as silicon wafers) will contain point defects across their surface, and any die containing such a defect is likely to fail. Making dies smaller means that the chance of any one die having a defect is reduced, and thus the yield of each wafer increases. Therefore, designs that use smaller dies stacked on top of each other can increase the yield from wafers and thus reduce the cost of ICs.

Finally, the ability to go vertically also opens up the semiconductor industry to customised semiconductor configurations. Designing and fabricating custom semiconductors is extremely expensive, which is why most products use off-the-shelf parts. However, it may be possible in the future for foundries to produce dies that allow engineers to mix and match dies to create custom configurations. For example, an engineer creating a custom mobile processor may choose low-energy dies and cellular modems, while an engineer designing a high-performance single board computer may combine a processor with a GPU and memory.

Overall, the 232-layer NAND IC demonstrates the power of going vertical, and it is exciting to see that miniature packages can now store data in terabytes. Of course, Micron will undoubtedly be unhappy with this number in a few days and will start developing a NAND device with even more layers, the things engineers will do…


By Robin Mitchell

Robin Mitchell is an electronic engineer who has been involved in electronics since the age of 13. After completing a BEng at the University of Warwick, Robin moved into the field of online content creation developing articles, news pieces, and projects aimed at professionals and makers alike. Currently, Robin runs a small electronics business, MitchElectronics, which produces educational kits and resources.

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