15-03-2022 | By Robin Mitchell
A consortium of semiconductor manufacturers and suppliers is creating an industry standard for interconnects between silicon chiplets. What challenges would a non-unified chiplet industry present, what is UCIe, and will it help accelerate future semiconductor developments?
The development of the System on Chip (SoC) enabled complex designs to be integrated onto a single die that offers cost advantages and reduces the overall size of a design. Combined with the ever-shrinking transistors, the result was the mass deployment of mobile processors leading to a wave of technological advancements in the form of mobile computing. Everything from tablets to smartphones has the SoC to thank, as, without it, such designs would be too complex and large to construct.
While the SoC has proven its worth time and time again, the continuing demand for new technology combined with the increasingly larger challenges faced with reducing the size of transistors is now seeing researchers look at alternative design methods for increasing device complexity. One of these ideas is the use of vertical stacking of dies in a 3D structure that allows transistor counts to increase without reducing the size of transistors. This is already being used en masse in flash devices that use vertically stacked structures in their silicon layer but is yet to be done for mainstream processors.
Another concept that is starting to gain traction is the use of chiplets, small silicon dies that are connected to create a more complex device. It is advantageous to use as little die area as possible when creating semiconductors for two reasons. The first is that using less die space means more devices can be fitted onto a wafer, and this increases the yield of each wafer. The second is that smaller die areas increase the overall yield as defects and mistakes in the wafer are less likely to occur in a die.
But while System on Packages (SoP) is already being developed, a potential industry can be formed from this that must be approached carefully. Looking into the future, it is clear that SoP will become the dominant technology for creating complex designs. Combining the dies of multiple manufacturers could allow for entirely custom packages whose construction is entirely automated (in a similar fashion to PCB population via Pick and Place).
However, splitting up a design across various dies comes with one major challenge; communication. A design split into different dies needs to use a communication method that is shared across all dies to ensure the highest bandwidth, lowest latency, and easiest connection possible. Having four dies from different manufacturers, all having different communication protocols, increases the complexity of an SoP and wastes semiconductor space as each bus protocol would need its own dedicated circuitry.
Recognising the potential challenges of a future where semiconductor manufacturers will most likely make their own inter-chip communication standards, some of the industry’s finest manufacturers have come together to agree upon a future standard for chip communication. The most prominent players in the consortium include Intel, AMD, ARM, TSMC, and Samsung, all of whom are trying to secure their technologies into the new standard.
Universal Chiplet Interconnect Express (UCIe) is a proposed interconnection standard that will describe both the physical and the protocol layer, which will be heavily based on CXL and PCIe as these are already widely used established bus protocols that are effective at low-latency high-bandwidth communication. The new standard will aim to reduce the time taken to design new packages, allow for smaller process technologies, reduce the costs of IP, and reduce a product’s SKU cost while enabling customisation.
It has also been suggested that the new standard will incorporate optical connections for high-speed data links to other dies not located in the package. One of the significant advantages of optical transmission is that it doesn’t require any transceiver as an LED sending light down a fibre optic merely requires a photodiode on the receiver connected to an amplifier that can easily be integrated into the die itself.
There is no doubt that SoP will become the dominant technology of the future. It removes the need to reduce transistor sizes to create the next generation of technology while also allowing customers to customise semiconductor products fully. The use of SoP will also reduce the cost of design as smaller dies with higher yields will undoubtedly be cheaper to produce, which will usher in a new era of semiconductor usage.
However, for future semiconductor devices to operate at their maximum efficiency, it will be crucial to develop a standard interconnection technology. Suppose manufacturers are allowed to develop their own protocols and connection hardware. In that case, it will lead to a fragmented industry that will hinder advances in technology and see many inefficient protocols be supported for years for the sake of backwards compatibility.