13-07-2021 | | By Robin Mitchell
Intel and AMD have recently announced that they will be the first customers of TSMCs 3nm process that is about to enter risk production. Why is Intel looking towards TSMC for 3nm devices, what details are known about TSMCs 3nm, and why are process node numbers quickly becoming insignificant?
While the concept of CPUs outdates Intel, it was Intel that first put an entire CPU onto a single chip (the Intel 4004). Since then, Intel has both designed CPUs and manufactured them in their own foundries, and this has arguably helped Intel remain at the forefront of semiconductor technology. Not only have they been able to design CPU hardware, but their understanding of the underlying fabrication process may have provided Intel with a competitive edge whereby they have been able to fully utilize their silicon (whether it be from short-cuts in the manufacturing process or unusual transistor arrangements).
However, this business model of tying the CPU technology to semiconductor technology has caused major drawbacks for Intel in recent years as they have struggled to create 7nm devices. As their CPU technology is tied to their process node, Intel's inability to deliver on 7nm devices meant that next-generation CPU technology was held back. Intel’s major competitor, AMD, has historically been behind Intel in CPU technology, but Intel’s inability to produce 7nm on time led to AMD taking the lead in CPU technology. Unlike Intel, AMD is a fabless company and relies on outsourcing its manufacturing to companies such as TSMC.
Recognizing the challenges of tying CPU technology to process node, Intel is now looking towards a future whereby CPU technology is not tied to process node. However, this alone is not enough for Intel to return to its former position as the world leader in CPU technology. For Intel to regain this title, they need to start delivering devices, and Intel now has no choice but to outsource some of their devices. As such, a recent report announced that Intel and Apple would be the first customers of TSMCs 3nm process.
It only seemed like yesterday that 7nm devices were being released to the commercial market. Despite the COVID pandemic, TSMC is already working on a 3nm process with an expected delivery date for commercial devices around the second half of 2022.
Currently, TSMC has released some details behind their N3 (3nm) process, and most of these figures are compared to their N5 (5nm) process. According to TSMC, the N3 process provides up to 70% logic density gain, a speed increase of 15% at the same power, and a 30% power reduction at the same speed compared to N5. Tape-out of devices are to be expected in 2021, but these are said to be risk production, meaning that there is no guarantee that devices produced will work or be produced in reliable quantities.
Other information released by TSMC also indicate that SRAM density is increased by 1.2 times, analogue circuitry density is increased by 1.1 times, and that the transistors used in the N3 process are of the FinFET variety. Furthermore, the 3N process is said to be targeting smartphone and high-performance computing applications. This makes sense when considering the power savings that mobile applications can take advantage of. In contrast, high-performance computing systems can take advantage of the logic density increase for more powerful devices operating at greater speeds.
It has been said by many in the industry that the concept of process nodes is becoming irrelevant, and trying to compare process nodes from different companies can be an unfair comparison. One piece of information released by Intel that strongly supports the irrelevancy of process node numbers is that Intel has hinted that it may relabel its chip process nodes to make it appear to be less behind than TSMC.
Historically, process nodes referred to the smallest length of a gate on a transistor, and the half-pitch (i.e. half the distance between two identical features), would also match this number. For example, the 250nm process would see all features having a minimum size of 250nm and a minimum distance of 250nm from each other.
However, these numbers no longer match, and the extremely small size of transistor features sees process nodes referring to almost anything the manufacturer decides. These numbers could refer to the minimum distance between two features, it could refer to the width of the gate channel, or it could refer to the minimum size of wire widths. Furthermore, process node numbers no longer directly refer to the capabilities of a device in terms of transistor density. For example, it has been said that Intel’s 10nm process is on par with TSMC’s 7nm process despite the supposedly larger number.
Overall, developers of semiconductors may need to start looking towards different figures that can better compare different devices. One figure that would provide a good metric would be transistor density which would indicate how much circuitry can fit onto a single device. This would work well with future chip designs that could stack multiple layers of logic; they may be constructed using a larger node process but might have a higher transistor density than those made using a smaller node on a 2D chip.