What is InFO? Xilinx puts UltraScale+ Into InFO Packaging from TSMC

30-03-2021 | By Robin Mitchell

Recently, Xilinx announced that it will be utilising Integrated Fan-Out (InFO) technology in its latest UltraScale+ product range. What will the upgrade enable, what is fan-out technology, and how does it help designs?

Xilinx Announces Use of InFO

Recently, Xilinx announced that it will be utilising TSMC packaging technology in InFO in its latest range of UltraScale+ devices. According to Xilinx, the increasing need for more powerful and smaller electronics is putting pressure on semiconductor designers to reduce the size of their components. As a result, the use of TSMC’s Integrated Fan-Out Technology (InFO), will help to achieve this goal.

The latest range of UltraScale+ devices are being targeted at cost-optimised designs, and the use of InFO technology will allow for increased DMIPS per unit area, and a form factor that is 70% smaller than other traditional integrated circuit designs. The Atrix UltraScale+ are devices that are designed with high I/O bandwidth and DSP capabilities in mind while the Zynq UltraScale+ devices are designed for low cost and low power operation. 

What is the InFO?

Integrated Fan-Out, or InFO is a technology developed by TSMC that expands from Fan-out wafer-level packaging. To understand how this type of packing technology works we first need to understand some of its predecessors.

Traditional ICs have been packaged epoxy, plastic, or ceramic materials that use a lead-frame which is bonded to the semiconductor die via bond wires. This construction method has been used since the first ICs and includes DIP, SOIC, and TQFP.

As electronics increased in popularity, there was a demand for smaller electronic components. This leads to extremely small profiles such as MLF and BGA packages, but even in these cases, the IC packaging itself is much larger than the die that is housed. Furthermore, these packages use long bonding wires which can degrade signal integrity, and thus causing issue with sensitive designs (i.e. high-speed, low-voltage).

To solve these issues, the industry developed Chip-Scale Packages (CSP), which effectively reduce the size of an IC to the same size as the die. Unlike traditional IC packages, the semiconductor directly connects to a circuit via solder balls thus eliminating the need for bond wires. While CSP packages are extremely small, they are often limited on the number of I/O as solder balls can only be so large. Such designs are sometimes referred to as Fan-In.

To solve the issue with limited I/O on Fan-In designs, Fan-Out packages increase the size of the final device, but provide more space for I/O to connect to. While this may appear to be a BGA, it is essential to recognise that there is a big difference between the two. A BGA device has a pre-cut die placed into the chip carrier and then bonded to connections whereas a Fan-Out device has the interconnection layers and pads grown on-top. This results in much shorter connections in a far smaller package.

In the TSMC process, the Fan-Out concept (InFO), has been expanded to integrate multiple dies on top of each other (such as a processor and memory), which share a common I/O connecting layer. To sum up Fan-Out packaging technology, silicon dies have their packaging grown onto them instead of being diced up and place into packages.

Image courtesy TSMC

Advantages of Fan-Out Packages

Fan-out packages offer designs a whole range of advantages when compared to typical ICs. The first is that the length of the conductor between the IC and PCB is minimised which helps with signal integrity. As a result, such devices can operate at higher frequencies as well as operate at higher currents.

The second advantage of using chip-scale packaging is that heat dissipation is more easily controlled, and the lack of packing moulding allows for direct contact between a heat sink and a semiconductor.

The third advantage of chip-scale packaging is the significant reduction in size which allows for the creation of small electronic devices. Furthermore, the use of 3D semiconductors with functional layers added on top of each other significantly increases the capabilities of the device.

However, there are some disadvantages to using a chip-scale package ICs. The first is that repairing such circuits can be extremely difficult due to the small size and potential for damaging the die. Like BGA, such devices require hot air and an extremely skilled hand to remove from a PCB.

The second disadvantage is entirely unobvious but can cause serious issues; light sensitivity. Some chip-scale packages expose the die directly, and as users of the Raspberry Pi 2 discovered, can undergo fault conditions when exposed to strong flashes of light (such as from a Xenon tube). The reason for this is that semiconductor devices undergo the photoelectric effect when exposed to light, and this can upset transistor states. As such, electronics using chip-scale packages can sometimes be left vulnerable to light. 

Read More


By Robin Mitchell

Robin Mitchell is an electronic engineer who has been involved in electronics since the age of 13. After completing a BEng at the University of Warwick, Robin moved into the field of online content creation, developing articles, news pieces, and projects aimed at professionals and makers alike. Currently, Robin runs a small electronics business, MitchElectronics, which produces educational kits and resources.