Moore’s Law – Let’s go up instead of down!

08-09-2020 | By Robin Mitchell

With Moore’s law coming to an end, silicon foundries are looking at inventive ways to continue the number of transistors on ICs. One way is to go up instead of down, so what are 3D ICs, are they in use, and what different methods for creating 3D chips exist?

Why Moore’s Law is ending

Moore’s law states that the number of transistors on an IC doubles every two years, and this has mostly held true since the introduction of the first integrated circuits. This doubling of transistors is what has mostly driven improvements in electronics, as the doubling of transistors not only improves performance with the ability to process more data but also leads to lower power requirements per computation. However, now that transistors are becoming atomic in scale (with some gates being as small as 20 silicon atoms across), making transistors smaller is a very difficult task, and cannot even be guaranteed. As a result, companies, such as Intel, which rely on reducing transistor sizes to bring out improved technology have had difficulties in bringing updated architectures, and thus holding the industry back by a number of years. 

Soon, transistors will become too small to reduce, and their physical limits will effectively stop transistor counts increasing on chips. However, all of this time, scientists have focused on going down to fit more transistors onto a die, and all transistors on a typical CPU exist in a 2D plane. What would happen if researchers take inspiration from Star Trek, and turn the chessboard into a 3D playing field? 

What are 2.5D ICs?

2.5D ICs are one solution for the inability to reduce transistor sizes, and essentially are multiple dies connected together via bond wires into a single package. Semiconductor dies themselves are incredibly small, and those that are large (such as those found in CPUs), house billions of transistors which his far more than enough for most applications. 

While 2.5D ICs do not go up, they can take advantage of incredibly small silicon dies, all of which can be used for different functions, and combine them into a single package. One of the biggest challenges faced with semiconductor foundries is the reduction in chip yield as a die becomes larger. The more dies that fit on a single wafer, the higher the chance that a die will succeed as point defects are less likely to affect individual dies. If large die designs can be broken down into multiple smaller chips, not only could IC yields increase, but they can easily be customised, and the use of automatic wire bonding machines helps to automate the process. However, even then, 2.5D designs do not go vertically and are still restricted to the 2D plane. 

What are stacked 3D ICs?

A 3D IC is one that builds up vertically, with active components (such as transistors) existing on-top of each other. Such technology can dramatically increase the number of transistors in a package as each layer effectively doubles the number of total devices. Stacking transistors also allows designers to focus on a set of different challenges instead of trying to further reduce the physical size of transistor features. Achieving 3D ICs can be done using multiple methods with the two most common being die-to-die and monolithic. 

A die-to-die stacked 3D IC would stack multiple dies on top of each other, and utilise either bond wires or vias to electrically connect the layers. A major advantage to such a construction method is that each die can be tested before being bonded, thus ensuring that only verified dies that function are used. This helps to improve the yield of 3D ICs, and therefore reduce the final cost.


What are 3D monolithic ICs? 

3D monolithic ICs are most likely the ideal goal for the industry to use due to their all-in-one construction method.A 3D monolithic IC is one that is grown in layers, exactly the same as typical ICs, and each active layer that holds transistors is deposited onto a single die. Instead of combining multiple dies, a monolithic 3D IC is one continuous piece of semiconductor, and interconnection layers bond various transistors in different layers together. 

This method has various manufacturing benefits when compared to other technologies, including the lack of a need for die alignment, silicon vias, or wire bonds. The manufacturing method also allows for continuous fabrication on a single wafer, and the final device is smaller than those using stacked dies. However, unlike other methods, 3D monolithic ICs are still years away, and only 3D FLASH technology can be considered to be the only commercial example of a 3D IC.


Going up instead of down is going to be the best result for the industry moving ahead unless an alternative semiconductor technology allows for either smaller transistors (unlikely), or those that can operate significantly faster. While building up has its challenges (heat dissipation for one would be a nightmare), it will allow for transistor counts to continue increasing, and in a world which is becoming more dependent on advantage multiprocessor applications, more cores will become incredibly important. 

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By Robin Mitchell

Robin Mitchell is an electronic engineer who has been involved in electronics since the age of 13. After completing a BEng at the University of Warwick, Robin moved into the field of online content creation, developing articles, news pieces, and projects aimed at professionals and makers alike. Currently, Robin runs a small electronics business, MitchElectronics, which produces educational kits and resources.