10-12-2020 | | By Sam Brown
Intel’s failure in the 7nm technology node has seen its competitors overtake in silicon technology, but Intel is still insistent on moving forward with its 5nm and 3nm plans. Why did Intel fall behind its competitors, what hurdles do manufacturers have to get over, and what will future silicon look like?
For the past few years, Intel has fallen their major competitor, AMD, with regards to processor technology, and the architecture being produced by Intel is as much as 5 years behind. This means that some engineers are switching over to AMD to produce the latest computers in order to keep their hardware as cutting-edge as possible.
The main cause for Intel’s short-comings is the business practice of linking their next-generation architecture with their next-generation process node. In other words, Intel has historically only brought out new processors when having successfully reduced the smallest features in their silicon manufacturing process.
This business model most likely arose in Intel as it both designs and manufactures silicon devices while many other companies either design or manufacture silicon devices. Even companies that both design and produce silicon devices are generally not so highly reliant on the reduction of feature size to produce more effective products. For example, an analogue IC may benefit from a node reduction, but a CPU (which relies on maximising the number of transistors), would massively benefit from a node reduction.
However, while this business model has been beneficial to Intel since its inception, reducing transistor size has become increasingly complex, and to Intel’s demise, had delays in bringing out 14nm, and a failure in the 7nm process. The resulting delays have caused Intel’s CPU architecture to be halted until the next node is ready for commercialisation.
Despite the failures in reducing silicon technology, Intel is in a business where failure is not an option. Thus, Intel has still announced that they not only intend to complete their 7nm process, they will continue to develop both 5nm and 3nm processes. While exact dates around the release of these nodes have not been disclosed, Intel is expected to release its 7nm technology by 2023 while also introducing a range of new products.
In the meantime, Intel is still to decide on whether to outsource its 7nm devices to TSMC who have already commercialised the 7nm node. Considering that TMSC is a competitor of Intel, the use of TSMC services would be embarrassing to Intel as it would be clearly stating to the industry that it is unable to match the technological capabilities of TSMC. While the exact process and equipment used by Intel are not known, TSMC utilises extreme UV lithography produced by ASML.
Each reduction in semiconductor technology brings about its own problems, but solving these problems becomes exponentially more difficult. Reducing the size of the first integrated circuits would require the development of more accurate stepper motors for step-and-repeat processes while reducing the next generation after this requires high-quality silicon and better control in oxide growth.
However, solving these issues is nothing by comparison to the problems faced by modern semiconductors trying to created devices with sizes as small as 3nm. To start, quantum mechanic effects become seriously problematic with electronics tunnelling all over the place, thus making insulators potentially ineffective. At this size, the wavelength of even the highest frequency UV light is still an order of magnitude greater than the size of individual features. This means that simply passing light through a mask does not work as expected.
The last major hurdle that semiconductor foundries will eventually face is the atomic nature of transistors; what is the fewest number of atoms that a transistor can be practically made out of? If this number is reached, then the ability to reduce the size of transistors is no longer possible, and it is at this point that technology will hit a wall if it does not design new ways to increase the power of systems.
When devices can no longer be reduced commercially, chip designers will have to deploy new ideas to continue the power of their devices. One method that is increasingly becoming popular is the use of chiplets; multiple dies in a single package connected together. This allows for more ICs to be combined into a single package while also increasing the total number of transistors that can fit in a single device.
3D stacking of dies together is another method for increasing the total number of transistors. To date, almost all devices are 2D in nature (except for modern NAND FLASH), whereby all transistors are laid out on a 2D grid. If, however, the vertical could be exploited, then each additional layer would significantly increase the total number of transistors in a single package (note the use of the term package instead of chip).
More exotic technologies that could help include memristors for creating neuromorphic AI chips, and light for ultra-fast, high-frequency data processing. However, these are more likely to fit niche applications, while mainstream commercial devices will utilise 3D and chiplet technologies.