26-05-2022 | | By Robin Mitchell
As transistor sizes continue to shrink, Samsung is expected to be the first foundry to roll out 3nm devices. What advantages does transistor size reduction provide, what technology drives Samsung’s new process, and when will 3nm be available to the public?
Ever since the development of the first electronic components, researchers and engineers alike have strived to reduce the size of electronic parts as much as physically possible. The most obvious advantage to making electronic components smaller is that it allows for designs to be made smaller or for more complex designs to be constructed in the same space. The same applies to semiconductors; by reducing the size of transistors, more transistors can be integrated onto the same area, allowing for more processors, hardware accelerators, and control circuits to be integrated.
However, there are additional advantages to reducing the size of transistors that are somewhat unique to semiconductors. Unlike capacitors and resistors, shrinking the size of transistors minimises the amount of power consumed using smaller switching currents and smaller gate voltages. Furthermore, these smaller voltages and physical sizes also allow for higher operating frequencies, which is especially advantageous for improving single thread processing (i.e., greater instruction throughput).
As such, the latest silicon technologies are generally geared toward processors that rely on either large core counts or low energy operation. It is rare to find standard off-the-shelf microcontrollers, sensors, or bus controllers using such technology as it is unnecessary.
It is no secret that semiconductors are by far the most advanced device manufactured by mankind, and the equipment needed to produce such devices surpasses that of many research facilities in complexity and price. It is also well known that the extreme complexities involved come with significant risk, and semiconductor manufacturers are now regularly facing delays and challenges never seen before. As such, semiconductor foundries are often highly secretive of their research, their capabilities, and the services that they provide.
Samsung is one of the very few semiconductor manufacturers capable of producing state-of-the-art semiconductors, and their recent announcement of 3nm production has the engineering world excited. While large portions of their capabilities are kept from the general public, general statistics on power consumption and transistor technology being deployed have been released.
Firstly, Samsung’s new 3nm process will utilise Multi-Bridge Channel Field Effect Transistors (MBCFET), which are gate-all-around transistors using nanosheets instead of nanowires. The use of a gate-all-around not only allows for physically smaller transistors but also provides better switching characteristics as the channel is entirely surrounded by the gate. Furthermore, the use of nanosheet layers for the channel allows for precise control over dimensions, resulting in less variation between identical transistors.
Secondly, the transistor gate pitch has been reported to be 40nm with an interconnect pitch of 32nm. While the technology may be called 3nm, it should be understood that this will refer to a specific feature (such as the width of the channel or the width of the gate). To ensure that transistors do not interfere with each other, gates and channels have to be separated by some distance.
Thirdly, Samsung released generic numbers regarding the improvements provided by 3nm compared to 7nm process technologies. According to Samsung, their 3nm node reduces power consumption by 50%, improves overall device performance by 30%, and reduces the total semiconductor area by 45%. Regarding transistor density, it is expected that the new node will allow for 202 million transistors per mm2.
Currently, 3nm is still in the research stages, but it is expected that risk production will begin in 2022. During this stage, commercial devices are manufactured, but customers are made aware of production risks that are not currently known. Once risk production has been done (proving the manufacturing process), it will then be released for all designs (most likely to happen between 2023 and 2024).
One risk that stands out with the new 3nm node is using a new transistor topology. Older improvements in transistor node would often use the same design style (such as 20nm FinFET to 14nm FinFET), and the risks associated with such a design and the equipment used to manufacture these designs is generally well understood. However, Samsung moving to a GAA transistor topology will see Samsung require drastically new manufacturing techniques. While these may be reproducible under laboratory conditions, it could be a very different scenario when trying to create entire wafers for mass production.
The new 3nm technology demonstrated by Samsung presents exciting new possibilities in the field of semiconductor design, and the use of GAA transistors will usher in a new generation of low-energy high-performance processors. But will the first batches of 3nm devices be successful, and if they are, will their yield provide customers with a profitable solution? Only time will tell.