12-03-2021 | | By Robin Mitchell
Recently, Kioxia and Western Digital announced the development of the 6th generation Flash memory, and the features that it incorporates. Who is Kioxia? What does the new memory offer, and how does it demonstrate stacked designs?
Engineers welcome the recent announcement from Kioxia and Western Digital, but while Western Digital is a well-known brand, Kioxia may be unfamiliar to many. Kioxia is a computer memory producer from Japan that spun off from Toshiba Memory. Founded in 2018, the company has 12,000 employees, has approximately 19% of the world’s share of NAND Flash sales, and operates worldwide.
Suppose it’s one thing that computers never seem to have enough of, its memory. Each time manufacturers announce the next generation of memory technology, increased memory sizes with higher access speeds are usually expected. The latest announcement from Kioxia and Western Digital do just this.
The joint development of the 6th generation Flash memory has resulted in devices with 162 layers using 3D memory technology. Such technology takes advantage of epitaxial growth of layers that allow memory cells to be oriented vertically instead of horizontally across a silicon die.
The new technology has seen advancements in construction technique and the ability to create memory devices that go beyond the standard eight-stagger memory hole array. It provides 10% greater lateral cell density (i.e. making memory bit-widths greater while making the physical memory towers narrower). However, despite the increase in layers from 112 to 162, the new technology results in a 40% reduction in the final die size.
The icing on the cake for the 6th generation technology comes with the use of Circuit Under Array CMOS technology. Traditional designs place control and power management circuitry around the memory footprint, but Circuit Under Array instead puts this circuitry on the silicon layer directly below the stacked memory array. As a result, the die can further be shrunk, but the proximity of the circuitry to the memory elements also increases the read latency performance by 10% while I/O is improved by 66%.
With all of these technological capabilities combined, the resulting memory devices have a lower cost-per-bit of up to 70% while increasing the overall memory size.
Moore’s Law has been, and continues to be, extremely important. The more devices and memory that can fit into a single device, the more it can do, and thus its capabilities are increased. At the same time, devices become cheaper and therefore more economical in a list of ever-growing applications.
But simply reducing the size of transistors on a silicon die is only one way for increasing the power of devices. This 6th generation Flash memory perfectly demonstrates how devices can go up as well as out to increase device capabilities.
Reducing a transistors used area by 50% essentially allows for twice as many transistors to fit for a given area. However, reducing transistors is becoming an increasingly difficult challenge as the size of transistors approaches the atomic scale.
But, if a whole new die layer is added above the die, then the number of transistors doubles while retaining the size of individual transistors. Such a device is considered 3D in nature as it makes use of all three dimensions to create active components, and its use is becoming increasingly popular.
Challenges that need to be solved include power dissipation and methods for growing silicon layers on-top of active components. Still, other alternative methods do exist including chiplets, modules, and stacked dies.