Cadence Design Systems now offers the Cadence Cerebrus Intelligent Chip Explorer, a new ML-based tool that automates and scales digital chip design, allowing customers to efficiently deliver demanding chip design goals. The combination of Cerebrus and the Cadence RTL-to-signoff flow provides advanced chip designers, CAD teams and IP developers the capability to improve engineering productivity by up to 10X versus a manual approach while also achieving up to a 20% better power, performance and area.
With the addition of Cerebrus to the broader digital product portfolio, the company provides the industry’s most advanced ML-enabled digital full flow, from synthesis through implementation and signoff. The new tool is cloud-enabled and utilises highly scalable compute resources from leading cloud providers to quickly meet design demands across a broad range of markets, including consumer, hyperscale computing, 5G communications, automotive and mobile.
“Previously, design teams didn’t have an automated way to reuse historical design knowledge, leading to excess time spent on manual re-learning with each new project and lost margins,” said Dr Chin-Chi Teng, senior vice president and general manager in the Digital and Signoff Group at Cadence. “The delivery of Cerebrus marks an EDA industry revolution with ML-driven digital chip design where engineering teams have a greater opportunity to provide higher impact in their organisations because they can offload manual processes. As the industry continues to move to advanced nodes and design size and complexity increase, Cerebrus lets designers achieve PPA goals much more efficiently.”
“To efficiently maximise the performance of new products that use emerging process nodes, digital implementation flows used by our engineering team need to be continuously updated. Automated design flow optimisation is critical for realising product development at a much higher throughput. Cerebrus, with its innovative ML capabilities and the Cadence RTL-to-signoff tools have provided automated flow optimisation and floorplan exploration, improving design performance by more than 10%. Following this success, the new approach will be adopted in the development of our latest design projects,” said Satoshi Shibatani, director, Digital Design Technology Department, Shared R&D EDA Division, Renesas.
“As Samsung Foundry continues to deploy up-to-date process nodes, the efficiency of our Design Technology Co-Optimisation (DTCO) program is very important, and we are always looking for innovative ways to exceed PPA in chip implementation. As part of our long-term partnership with Cadence, Samsung Foundry has used Cerebrus and the Cadence digital implementation flow on multiple applications. We’ve observed more than an 8% power reduction on some of our most critical blocks in just a few days versus many months of manual effort. In addition, we are using Cerebrus for automated floorplan power distribution network sizing, which has resulted in more than 50% better final design timing. Due to Cerebrus and the digital implementation flow delivering better PPA and significant productivity improvements, the solution has become a valuable addition to our DTCO program,” quoted Sangyun Kim, vice president, Design Technology, Samsung Foundry.