How Intel’s Backside Power Reduces Power Consumption in Future Chips

As semiconductor foundries tackle the challenges of transistor miniaturisation, researchers are exploring new materials and techniques to enhance next-generation chip performance, a key focus in the evolving landscape of advanced semiconductor technology. Now, Intel is getting ready to offer its latest range of technological innovations through its backside power connections, which help reduce power losses and increase device performance. What challenges does traditional power delivery face in semiconductors, how does the new backside power delivery method work, and what other methods will be deployed in future devices?

What challenges does traditional power delivery face in semiconductors?

Integrated circuits have undergone numerous changes ever since the first devices were rolled out more than 60 years ago. With each new generation of chips, transistors are made smaller and faster, which incidentally results in them consuming less power. 

However, this transistor scaling leads to more components being integrated into the same space, resulting in increased overall power consumption, a critical issue in high-performance computing. This is why high-density devices such as CPUs and GPUs progressively consume more power with each new family; it is not uncommon for a modern desktop CPU to now consume more than 100W.

Navigating Power Consumption Challenges

Delving deeper into the power consumption conundrum, it's not just about packing more transistors into a chip. We're seeing a fascinating shift in the semiconductor industry towards innovative materials. Intel's foray into novel semiconductor compounds is a game-changer, aiming to tackle the inherent resistance in conductive paths. This isn't just a technical tweak; it's a stride towards redefining chip efficiency and performance, a move that could reshape our expectations of semiconductor capabilities.

While high power consumption is manageable in larger chips, allowing for effective heat distribution and the use of large heatsinks, it becomes a significant challenge in compact semiconductor designs, such as those used in mobile devices and IoT applications. But as chips are also being reduced in size, the heat density of such devices is so great that cooling can be challenging and, in some cases, require liquid cooling mechanisms. This is also problematic for compact designs (such as server racks), as there is little space for large heatsinks. 

Thus, chip makers have to try to identify sources of power consumption and attempt to either eliminate them outright or reduce them as much as possible. For example, the natural resistance of conductive paths results in a small amount of energy loss which directly generates heat, so chip makers can try to reduce the overall length of conductors used as well as choosing materials with a lower resistance.

Another option is to target the speed at which devices operate, as dynamic power consumption rapidly increases with frequency. Of course, reducing device speed directly impacts performance, so chip makers will often incorporate low-power modes that shut down performance cores or reduce core speeds when idle. 

But one area that is particularly troublesome to solve is power delivery. Typical planar devices start with the active layer, which includes transistor structures and doped regions. 

The next layer after this first layer includes the gates to these transistors as well as crucial interconnects between transistors, and the next layer after this is the first metal layer that forms additional interconnects. With each new layer, the width and thickness of the interconnects increases to reduce power consumption and improve performance.

However, while this design method has worked well in the past, there is a unique problem that sees a substantial amount of power loss: power trace length. Simply put, as power connections need to start at the top layer, every single transistor that is connected to a power rail needs to have numerous vias between each layer as power connectors start from the top and work their way down into the first layer. 

With each change in layer, the reducing width of connectors increases resistive losses, and the use of vias see boundaries forming between layers which itself induces additional losses. This also means that heat dissipation from power lines also spreads into the rest of the chip, including the interconnects used for handling signals. 

Peering into the layered complexity of modern chips, it's clear that the traditional approach to power delivery is becoming a bit of a tightrope walk. As we cram more into these silicon marvels, the challenge isn't just about managing power but also about mastering the art of heat management. It's a delicate balance, one that Intel seems to be addressing head-on with their innovative backside power delivery. This isn't just about keeping things cool; it's about rethinking how power interacts with every part of the chip, ensuring that performance doesn't get lost in the heat of the moment.

Intel’s response – Backside Power

Recognising the challenges faced with typical planar technologies, Intel demonstrated its achievement in developing a new power delivery mechanism that they say will help to reduce power losses as well as being essential for future 1nm nodes. The new concept, being dubbed Backside Power & Direct Backside Contact, deviates from traditional designs in that all power connections are made from the underside of a wafer instead of being on top.

This use of a backside design means that power connectors do not need to weave around signal lines and instead connect directly to the underside of transistors. Not only does this significantly reduce the length of power lines, but it also reduces the number of vias needed to get power into transistors. This design also allows for power connectors to remain wide and thick, thereby reducing resistive losses. 

The new concept has also been paired with a Direct Backside Contact, which exposes contacts at the underside of the chip instead of bringing all contacts to the top side of the chip. Not only does this help to increase contact density (as power connectors are no longer needed on the top side), but it also helps to separate power and signal lines, which can improve signal integrity. 

What other methods could be deployed going forward?

As the feature sizes on modern devices approach the sub-nanometre world, engineers will need to deploy all kinds of unique solutions to solve the challenges faced. While silicon has proven itself to be a highly suitable semiconductor for modern applications, it is possible that it will be replaced by other contenders in the far future. 

One such candidate could be graphene as not only can it be made to have superconductive properties but can be easily manipulated to produce all kinds of unique abilities, including the formation of complex 3D structures capable of trapping particles needed for quantum computing. However, as graphene is notably difficult to manufacture on scale, it is far from being a viable replacement for silicon in the near future.

Looking ahead, the future of semiconductor design is set to embrace chiplet architecture, where an integrated circuit package comprises multiple smaller chips, a trend gaining traction in advanced electronics manufacturing. Not only does this give engineers plenty of design flexibility, but it can also help reduce power consumption as only circuits that are absolutely needed are integrated into the design.

Custom silicon devices, such as those demonstrated by Apple, could also become increasingly important. As custom silicon devices only integrate circuits that are absolutely needed for a design, they always give the best performance per watt compared to any off-the-shelf solution.

There are so many techniques that engineers can deploy into semiconductors to try and reduce energy consumption, meaning that we can expect to see all kinds of exciting technologies in the years to come. However, what can be said about the introduction of backside power delivery is that it introduces an entirely new concept that could very well change how chips are made in the future. 

Broadening Horizons: The Industry-Wide Impact of Semiconductor Innovations

When we look at the advancements in semiconductor technology, particularly Intel's backside power delivery, it's not just a leap for chip manufacturing; it's a catalyst for transformation across multiple industries. From the automotive sector, where efficient power management is key to the evolution of electric vehicles, to healthcare, where enhanced chip performance can revolutionise medical devices and patient monitoring systems, the ripple effect is immense.

Consider the realm of artificial intelligence and machine learning. Here, the demand for high-speed, efficient computing is insatiable. Innovations like backside power delivery and chiplet designs are not just improving existing systems; they're paving the way for more advanced AI algorithms, capable of faster processing and more complex tasks, all while consuming less power. This is crucial as we edge closer to realising the full potential of AI in everyday applications.

Looking towards the future, these semiconductor breakthroughs hold the promise of enabling technologies that are currently in their nascent stages. Quantum computing, for instance, stands to benefit immensely from these advancements. The ability to manage power and heat more effectively in chips could be a key factor in overcoming some of the current barriers in quantum computing development.

It's a thrilling time to be in the field of electronics. The innovations we're seeing today are not just about making devices smaller and more efficient; they're about opening new doors, exploring uncharted territories, and redefining what's possible in technology and beyond.