12-10-2021 | | By Robin Mitchell
Recently, NIST developed a new technique that allows them to determine faulty transistors that can also count the total number of defects. What challenges do large scale integrated circuits face, what did the NIST develop, and how can it help semiconductor producers in the future?
Increasing the number of transistors on a silicon die almost always requires a reduction in transistor size. Since the first integrated circuits, the reduction in transistor size required better lenses, new masks, and a shorter wavelength of light. However, as transistor features reach the individual nanometers, engineers have had to overcome challenges never seen before, including quantum effects, resolving images smaller than the wavelength of light being used, and growing nanolayers.
One problem that can hinder yield rates from semiconductor wafers is point defects. During the semiconductor production process, individual points in the single crystal can be defective for several reasons, including a void, a contaminant, or a dislocation in the crystal structure. Large-scale transistors are rarely affected by point defects due to the small size of the defect relative to the transistor. However, transistors whose size is similar to a defect will be severely affected and may not function correctly.
This may not be a challenge for a chip with ten transistors, but modern devices can now have transistors numbering in the billions. If just a single transistor operates incorrectly, the entire design may not function, and as the number of transistors increases, the chances of just one failing increases too. To make matters worse, some transistors that fail to function may go unnoticed during the testing period, which could affect products down the line that are reliant on the device’s proper functioning.
Recently, researchers from the National Institute of Standards and Technology (NIST) have developed a technique that can identify the type of defects in a transistor and count the number of defects. The new method focuses solely on defects found in the transistor channel, and this was chosen as the channel is often the most sensitive part to defects.
Currently, engineers can detect faulty transistors using current analysis, but these methods do not allow for counting the various types of defects that can occur. To solve this, the NIST used a method called Electrically Detected Magnetic Resonance (EDMR), which is similar to MRI found in hospitals.
Simply put, defects in a crystal structure interfere with electron flow and create an area that is neutrally charged via recombination. The transistor is then exposed to microwave radiation as well as a strong external magnetic field. Defects in the transistor will interfere with the current flow at very specific combinations of microwave frequency and magnetic strength. This can be used to determine the type of defect in the transistor.
Furthermore, the team utilized a technique called bipolar amplification effect (BAE) to specifically target the channel of a transistor. The use of BAE enables the researcher to overcome shot noise caused by the recombination of holes and electrons at low currents. Overall, combining the two methods enabled the researchers to determine the type of defects and their number.
One of the more obvious applications for determining the type of defects and their quantity is the ability to compare the production method of the initial crystal ingot and the resulting success rate. Despite the strict conditions used to produce ingots, slight variations between different wafers still exist, which could depend on controllable environmental factors.
Understanding the types of defects present, where they are, and their total number could also prove useful for future designs that incorporate redundant circuitry. For example, a multicore CPU could integrate 20 cores, and those that are defective can be disabled.
However, some defects may be passable, and thus cores that would typically be deactivated could instead be used.
Another potential use of such testing is to predict which areas in a wafer could be problematic and plan wafer production accordingly. However, this would require a new testing method to test the entire wafer before it enters production.
While the current testing method is still confined to a laboratory, it shows real promise in the field of semiconductor testing.