A new method for creating highly efficient gates in semiconductor wafers

07-09-2021 | By Sam Brown

Recently, researchers have developed a method for creating gates in FET transistors by adding the gate layer during wafer production. What challenges do small transistors present, what did the researchers do, and could this lead to a new method for building semiconductors?

Why are semiconductor layers challenging?

Almost all semiconductors manufactured are built in layers that come together to create a functional device. Such layers include an insulation layer to separate the gate from the transistor’s channel, metal layers for interconnection, and layers to connect different metal layers.

When reducing the size of transistors, all these layers are physically reduced in size in all dimensions. This poses several challenges that can reduce the yield of a wafer (i.e. the number of successful devices on a single wafer). One challenge is that more minor features are harder to image due to physical limitations such as diffraction, reflection, and refraction. Another challenge faced by reducing the size of semiconductors is that fitting more transistors into any given area will result in increased failure counts due to point defects in the wafer.

Another problem that is rarely mentioned is the challenges of growing thin layers on top of wafers. Specifically, adding layers such as gates on top of oxide layers presents challenges as any foreign debris (dirt, grease etc.), will prevent adhesion between the layers and interfere with the gate’s electrical properties.

Researchers develop single-crystal semiconductor structures

Recently, researchers have demonstrated a new manufacturing method that could counteract the challenges of creating gate and insulation layers on semiconductors. Their method creates a semiconductor structure where the gate layer and body are a single crystal structure.

The method involved a layer of epitaxial aluminium being grown onto the wafer before the wafer is removed from the growth chamber. However, what isn’t clear in the report is whether this layer is added during the drawing of the single crystal silicon ingot or after the dicing process, which creates individual wafers. Considering that the term epitaxial is used, it is most likely that the team grew the layer on top of a wafer in an epitaxial furnace, which ensures that the wafer’s surface is clean and free from defects.

The researchers then compared their single-crystal devices against devices using standard deposition technologies. The results from the tests show that the single-crystal device has a 2.5x increase in conductivity due to reduced surface-charge scattering (caused by boundaries between different layers). The researchers also demonstrated how their single-crystal device could be patterned to create MEMS-like structures, which could help develop quantum devices.

Could such devices be the future of semiconductors?

It should be understood that this construction method is ideal for very small transistors and may be a requirement for creating devices below the 1nm mark. Typical ICs such as audio amplifiers, motor controllers, and logic controllers are unlikely to need such technology (due to their large transistor sizes). As transistor features in high-end devices continue to reduce in size, effects such as charge scattering will become a problem that traditional manufacturing techniques won’t cope with.

the use of epitaxially grown gates will likely become commonplace in the semiconductor industry, and computational devices may deploy such technology in the years to come.

By Sam Brown