12-05-2021 | By Robin Mitchell
Recently, Antmicro announced the release of its ARV module that integrates a RISC-V-based SoC and other supporting components. So what is RISC-V, what features does the new SoM contain, and is RISC-V about to explode?
What is RISC-V?
RISC-V is an open-source ISA that is jointly developed by researchers around the world with the University of California, Berkley, being the most predominant member. Before introducing RISC-V, most processor architectures such as x86 and ARM were (and still are), closed-sourced and proprietary. This means that anyone who wants to create a processor that is compatible with that ISA is required to seek a license from the patent holders.
While there are many architectures on the market, most of these cover microcontrollers and rarely make their way into everyday computing applications such as office and data centres. As such, the market is dominated by proprietary ISAs that can only be developed by the original patent holders (in this case, Intel, AMD, and ARM).
However, in 2010 researchers from the University of California conceived the idea of developing an open-source ISA that would allow anyone to create their own processor without the need for licenses or royalties. Thus, after several rounds of development, RISC-V was born, and the open-source nature of RISC-V allows any manufacturer to create a RISC-V compatible CPU.
Antmicro Releases RISC-V SoM
Recently, Antmicro (who has been involved with RISC-V development) announced the development of a new System-on-Module (SoM); the ARV Module. Powered by the StarFive 71x0 SoC, the SoM integrates all the major components needed to run a RISC-V computing system. In addition, the modular design allows the SoM to be easily inserted into designs.
The core of the new SoM is the StarFive JH7100 SoC which integrates two RISC-V cores with a maximum clock frequency of 1.5GHz. Also integrated into the SoC is a Tensilica Vision VPS DSP, NVLDA engine (for 1024MACs @ 500MHz), VPU with H264 and H265 at 4K at 60fps, Audio DSP, and TRNG and OTP security.
Connectivity is provided with DSI, CSI, HDMI, Gigabit Ethernet, dual ISP, and USB3.0 while the next release of the SoC will also integrate PCIe. However, the nature of the SoM means that there are no physical connectors (such as USB sockets), but instead, the signals are routed to contacts. Furthermore, the new SoM is compatible with the Antmicro Scalenode platform and is pin-compatible with the Raspberry Pi 4 Compute Module.
What does this development tell us about RISC-V?
The release of the SoM by Antmicro indicates two major shifts in the industry; the potential adoption of RISC-V and SoM in designs.
One of the biggest challenges faced with any new processor architecture is the lack of software and hardware support. For example, when RISC-V was introduced, there were no compilers in any language, not even an assembler. Of course, compilers are now becoming available in many common languages such as C and C++, but operating systems are still yet to support RISC-V. There are some Linux distributions that support RISC-V, but these are fringe operating systems that are not widely adopted. Therefore, you will not find RISC-V entering the home computer market anytime soon.
Now that Antmicro is developing an SoM using the RISC-V architecture, it enables designers to start experimenting with the platform as well as developing software solutions. However, the open-source nature of RISC-V may lead to cheaper processors which could provide engineers with an incentive to adopt. Therefore, RISC-V could become a major competitor against ARM as more designers move away from proprietary systems in favour of open-source platforms.
The packing of the RISC-V in an SoM presents engineers with multiple advantages and benefits the RISC-V movement. Firstly, the use of an SoM minimises the complexity in designing both prototypes and final designs as the SoM integrates all the major system components into a single package. Secondly, an SoM is potentially reusable, and if seated in a connector, can be interchanged with newer versions which simplify future upgrades. However, by far and large the most advantageous use of the SoM is that it will accelerate the development of RISC-V software.
Imagine the scenario where a new processor that provides many benefits was only available in chip form. Engineers who want to use the new platform would need to read the data sheet, learn how to connect it to other components, figure out how to route high-speed data lines, and then have the final product manufactured. In this scenario, the adoption of the new platform would be slow, and the lack of pre-made modules could even kill the movement altogether.
However, the new SoM allows engineers to test the new RISC-V architecture in no time at all. Only engineers who have already built a working system who want to reduce the size of their design need to worry about how to connect the processor to external circuitry physically.