Less will be Moore, but it wont come cheap

08-03-2018 | By Paul Whytock

The road to 3nm may well be paved with good, groundbreaking technical intentions but there are some pretty deep financial potholes that need to be negotiated on the way.

So when news breaks that the industry’s first 3nm test chip tapeout has been achieved it is an attention grabber and certainly could perpetuate the scaling predictions of Moore's Law.

But the harsh financial facts involved in turning 3nm into a feasible production reality make grim reading for the moneymen counting the beans at wafer fabrication companies.

Take the Taiwanese Semiconductor Manufacturing Corporation (TSMC) for example. It's costing that company a cool $20 billion to build a manufacturing unit capable of producing 3nm devices.

The thing is that creating smaller chip geometries means cramming increasingly high numbers of transistors into shrinking spaces and there are only a handful of companies with wallets of sufficient size to cope with the costs involved with that. Amongst those are the likes of Samsung, Intel, TSMC IBM and STMicro.

But despite the cost, TSMC is pretty bullish about its 3nm prospects and expects to be in production in about four years. But back to that news about the industry’s first 3nm test chip tapeout. It is the result of collaboration between Cadence Design Systems and nanoelectronics research organisation Imec.

The tapeout was completed using extreme ultraviolet lithography (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence Innovus Implementation System and Genus Synthesis Solution.

A 64bit CPU was used for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. The 3nm implementation flow was fully validated.

Imec believes that as process dimensions reduce to the 3nm node, interconnect variations become more significant. For the Cadence/Imec project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions.

There is no question that EUV is a radically different method to what’s been used before and it's understandable that a consequence of that is the generation of new technological problems, in addition to the more usual ones that come with trying to reduce process nodes while cramming more transistors together.

But one of the advantages with EUV is that many industry experts believe it is cost efficient which is a very welcome attribute given the huge overall financial commitment associated with designing and producing 3nm technology; costs that are exacerbated given the fact that as chip size shrinks, product defects that had an insignificant impact in the past will only add further expense to the financial investment demanded by 3nm.

But two inevitable results of all the efforts to make 3nm a reality are that Moore's Law will continue to have relevance and that eventually economies of scale will reimburse all the hefty financial pioneering that went into it.


By Paul Whytock

Paul Whytock is Technology Correspondent for Electropages. He has reported extensively on the electronics industry in Europe, the United States and the Far East for over thirty years. Prior to entering journalism, he worked as a design engineer with Ford Motor Company at locations in England, Germany, Holland and Belgium.