Aldec, Inc has updated its linting tool ALINT-PRO to enhance the support of Microchip Technology’s Libero SoC Design Suite. The new release supports automatic conversion of Libero projects into its environment for static linting and clock domain crossing analysis of hardware designs in VHDL, Verilog or SystemVerilog.
Static linting assists in detecting a wide variety of design issues, incorporating poor coding styles, improper clock and reset management, simulation versus synthesis mismatches, incorrectly implemented finite state machines, and other typical source code issues throughout the design flow. CDC (clock domain crossing) analysis is critical to designs with multiple asynchronous clocks and assists mitigate non-deterministic issues such as data incoherence because of metastability that inevitably appear in today’s large FPGA and SoC FPGA designs.
“The use of advanced verification tools such as static linting and CDC analysis can significantly reduce the number of non-trivial bugs escaping into production, save engineering resource and more importantly, increase the reliability of FPGA and SoC FPGA designs,” said Louie De Luna, director of Marketing at Aldec. “We’ve had a long-standing and successful partnership with Microchip FPGA business unit since 1987 and we’re happy to continue our relationship and provide value to their users.”
“FPGA designs are increasing in size and complexity requiring earlier detection of language and structural errors”, said Joe Mallett, senior marketing manager at Microchip. “Designers using Libero SoC Design Suite can take advantage of Aldec’s ALINT-PRO to help detect functional errors earlier in the FPGA design cycle.”
Together with the latest release of ALINT-PRO, Aldec and Microchip will be holding a webinar on 2 March 2023 – Linting and CDC Analysis for Microchip FPGA Designs.