New HES board ideal for prototyping and emulating ASIC and SoC designs

23-07-2021 | Aldec | Design & Manufacture

Aldec, Inc has launched the HES-VU19PD-ZU7EV, an ASIC/SoC physical prototyping and hardware emulation board that can contain designs of about 83M ASIC gates in size.

Compared to boards of a similar capacity, the device utilises only two FPGAs to provide logic. This simplifies FPGA partitioning and decreases project bring-up time for designs targeting a medium-sized ASIC or SoC. For larger designs, four boards can be joined through a high-speed backplane to provide the equivalent of about 332M ASIC gates. It will also be possible to connect backplanes together (up to three) to cater for designs of about 996M ASIC gates.

The device’s logic module FPGAs are both Virtex UltraScale+ VU19P devices, Xilinx’s highest logic capacity FPGA to date. The company's new HES board also offers a Xilinx Zynq UltraScale+ ZU7EV MPSoC. It serves as the host module and has a quad-core ARM Cortex-A53, dual-core ARM Cortex-R5 real-time processing units and PCIe Gen3 embedded IP.

“Our latest Virtex UltraScale+ VU19P device is naturally geared for ASIC and SoC prototyping,” said Chris Stinson, senior director of Test, Measurement and Emulation Markets at Xilinx. “Aldec’s inclusion of two of these devices, along with one of our most powerful Zynq FPGAs, has resulted in an extremely versatile platform that will enable designers to fast-track their ASIC and SoC projects.”

Zibi Zalewski, general manager of Aldec’s Hardware Division, comments: “For this new platform, we’ve replicated much of the system architecture of our popular dual FPGA boards in our HES-7 family and incorporated the newest and largest UltraScale+ FPGAs from Xilinx to greatly extend the capacity and functionality for both emulation and prototyping scenarios. Also, our use of the Zynq US+ device as a controller means it can host the testbench for prototyping. Indeed, the prototyping and emulation capabilities of our HES boards is unique to Aldec.”

Zalewski goes on to indicate that a revision to HES-DVM, Aldec’s fully automated and scalable hybrid verification environment for SoC and ASIC designs, is in the pipeline. He adds: “That will further unleash the power of the new board, through enhanced debug capabilities, for example.”

By Natasha Shek