Collaboration enables easy adoption of integrated digital full flow

16-07-2021 | Cadence | Design & Manufacture

Cadence Design Systems and United Microelectronics Corporation announced that the Cadence digital full flow has been optimised and certified for the UMC 22ULP/ULL process technologies to speed consumer, 5G and automotive application design. The flow, which includes leading implementation and signoff technology for ultra-low power designs, allows mutual customers to achieve top-quality designs and deliver a faster path to tape out.


The digital full flow that has been optimised for use on UMC’s 22ULP/ULL process technologies includes the Innovus Implementation System, Genus Synthesis Solution, Liberate Characterization, Quantus Extraction Solution, Tempus Timing Signoff Solution, Litho Physical Analyzer and Physical Verification System.


“Our 22ULP/ULL platform is ideal for a wide variety of semiconductor applications, including power- or leakage-sensitive consumer chips and wearable products that require longer battery life,” said Y.H. Chen, director of the IP Development and Design Support Division at UMC. “By collaborating with Cadence, we’re providing access to our latest process technologies and Cadence’s robust digital full flow, which enables our customers to meet stringent design requirements and achieve design and productivity goals.”


“Through our latest collaboration with UMC, our mutual customers can adopt our certified digital reference flow and UMC’s 22ULP/ULL low-power technologies and begin design work immediately,” said Kam Kittrell, senior product management group director in the Digital and Signoff Group at Cadence. “This certification allows UMC customers to leverage the most advanced low-power tool feature sets for synthesis, place-and-route, and signoff, enabling customers to design innovative applications with confidence.”


The digital full flow offers customers a fast path to design closure and better predictability. It supports the company’s Intelligent System Design strategy, enabling advanced-node SoC design excellence.

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