Cadence Design Systems has expanded its Tensilica Vision DSP product family with the launch of two new DSP IP cores for embedded vision and AI. Packing an industry-leading 3.8TOPS, the flagship Cadence Tensilica Vision Q8 DSP gives 2X performance and memory bandwidth in comparison to the Tensilica Vision Q7 DSP and energy efficiency for high-end vision and imaging applications in automotive and mobile markets. The DSP is optimised for always-on and smart sensor applications in the consumer market, offering an energy-efficient solution.
Based on the similar SIMD and VLIW architecture seen in its existing DSPs, the Vision Q8 and Vision P1 DSPs provide an N-way programming model that preserves software compatibility for a simple migration from its prior-generation DSPs with different SIMD widths. Like the rest of the Tensilica Vision DSP family, the Vision Q8 and Vision P1 DSPs support Tensilica Instruction Extension (TIE) language, enabling customers to customise the instruction set. Both DSPs also support XNNC and the NNAPI for neural network support. Also, they support more than 1700 OpenCV-based vision library functions, OpenCL and the Halide compiler for computer vision and imaging applications. Both cores are automotive-ready with ASIL B hardware random faults and ASIL D systematic fault certification.
“The sheer number of sensors, as well as demands for higher frames per second and resolution, are driving the need for high-performance vision and AI DSPs that support a variety of data types,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “At the same time, the market also needs low-power vision DSPs with entry-level AI support for always-on smart sensor applications. With the introduction of the Tensilica Vision Q8 and Vision P1 DSPs, Cadence offers our customers optimal flexibility and faster time to market with a comprehensive portfolio of vision and AI DSPs from the high end to the low end.”