High-performance MCUs offer maximum theoretical performance of the Cortex-M7

03-08-2015 | Farnell element14 | Semiconductors

The STM32F7 series of high-performance MCUs with ARM Cortex-M7 core is now available from Farnell element14. The device takes advantage of STMicroelectronics' ART Accelerator as well as an L1 cache to deliver the maximum theoretical performance of the Cortex-M7, says the company. This superlative performance is achieved regardless of whether the code is executed from embedded Flash or external memory: 1082 CoreMark /462 DMIPS at 216 MHz fCPU. The STM32F7 is fully pin-to-pin and code compatible with the STM32F4 and the STM32 ecosystem, allowing for easy upgrade of existing designs. System performance is optimised by combining brand-new peripherals around the Cortex-M7 with a superior interconnect architecture featuring AXI and multi AHB bus matrix, multiple DMA and the Chrom-ART Accelerator hardware. This enables concurrent high-speed data transfers between bus masters and slaves without overworking the CPU. The large SRAM with overloading architecture provides support for large data buffers, critical real-time data routines and backup. It consists of 320 Kbytes, including 64Kbytes of Data TCM RAM; 16 Kbytes of instruction TCM RAM and 4Kbytes of backup SRAM. New peripheral sets include two SAI (with SPDIF outport support), three 12S half-duplex and SPDID input, enabling multiple audio channel I/O support; 2x USB OTG with dedicated power supplies, supporting USB communication even when the MCU is powered at 1.8V; dual QuadSPI interface to connect cost-effective memories with 1, 4 or 8 data pins, says the company.

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