Advancing photonic package design to address key data centre challenges

Sarcina Technology has reported advances in its photonic package design capabilities for Co-Packaged Optics (CPO), addressing fundamental challenges faced by data centres in dealing with the rapidly increasing amount of data as AI evolves. The company's pioneering work in photonic package design is facilitating a new era of high data rate, high bandwidth, and low power interconnects.

Traditional copper interconnects can no longer meet the performance, power and density demands of next-generation data centre systems. Copper interconnects become inadequate when the signal travelling distance exceeds a few metres due to excessive insertion loss in copper cables. System architects are now moving towards optical integration at the package level due to higher bandwidth, lower latency, energy efficiency, space savings, and longer transmission distances.

According to Larry Zu, CEO at Sarcina Technology: "Our new approach to Co-Packaged Optics removes the long copper trace between the switch and the optical module, replacing it with short, high-integrity connections between ASIC and optics. This is made possible because of our unique package design skills, creating novel layout architectures and integration schemes that directly integrate switch ASICs to photonic ICs inside a package. As the recent rise in AI applications puts more and more pressure on data centre systems, the need for this expertise has never been greater."

The company's design approach is rooted in four key disciplines: electrical performance, optical alignment, thermal control, and mechanical robustness. Its packaging solutions are carefully architected to achieve the following:

• High signal integrity under a high data rate of transmission
• Power integrity simulation
• Thermal management and mechanical reliability
• Compact optical integration
• Long-term system durability

The company's design portfolio includes full-package architecture for integrating photonic and electronic components in a single module:

• Co-Design: Seamless integration of PICs and ASICs with optimised placement, signal routing and thermal dissipation.
• Opto-Electronic Interface Engineering: Coordinated electrical and optical layout, ensuring clean transitions and minimal loss, verified via high-speed signal integrity simulation across package layers and interfaces.
• Multi-Chip Module (MCM) Layout: Architecting packages that bring together ASICs, modulators, drivers, TIAs and passives in the form of bare dice or chiplet, packaged ASICs from different package types and in unified 2.5D or 3D layouts.
• Precision Optical Coupling: Developing alignment strategies and mechanical structures that support micron-accuracy fibre and lens placement within package constraints.

Larry Zu concludes: "Sarcina's expertise in both high-speed electrical packaging and Co-Packaged Optics with Silicon Photonics chiplets sets us apart. This is particularly valuable as the industry shifts toward co-packaged solutions to improve data transmission efficiency and reduce power consumption. By seamlessly integrating multiple ASIC dice with optical components, Sarcina addresses challenges facing data centres that traditional semiconductor or optical companies might struggle with. It's exciting to see how this kind of cross-disciplinary capability can shape next-generation connectivity and computing solutions."