Huawei UB-Mesh: Replacing PCIe and TCP/IP in AI Data Centres

As computing workloads scale and diversify, particularly in fields such as AI, high-performance computing, and large-scale data processing, the infrastructure used to connect core components is coming under increasing scrutiny. The traditional ecosystem of buses, bridges, and protocols has evolved incrementally over decades, resulting in a fragmented web of legacy interconnects that limit performance, efficiency, and architectural freedom.

This article explores the technical constraints imposed by existing hardware links and buses, how they shape the design of today’s systems, and what a unified alternative might offer. With Huawei's UB-Mesh positioning itself as a comprehensive interconnect protocol for AI-era data centres, the question becomes: can this approach offer a meaningful step beyond PCIe, NVLink, and Ethernet, or will legacy standards continue to define the limits of system performance?

The Challenges with Modern Hardware Links and Buses

Modern computers are remarkably complex, filled with a labyrinth of bridges, buses, and interconnects designed to get hardware components to work together. At first glance, this might seem like a natural consequence of progress, but it comes with deep-rooted challenges.

If you step back to the era before the IBM PC, CPUs were simple devices, designed to handle straightforward tasks with minimal overhead. Complexity exploded as hardware flooded the market, and engineers needed practical ways to connect a wide variety of devices. The problem was compounded by the sheer size of the industry: thousands of engineers were creating their own methods for interfacing components, while CPU and silicon manufacturers scrambled to make their chips compatible with this growing variety of standards.

The result is the tangled ecosystem we see today: PCIe, USB, ISA, parallel ports, serial ports, and countless other interfaces, each solving a problem at the time but leaving a legacy that persists. Even high-performance servers, GPUs, and AI accelerators continue to rely on these standards, often out of necessity rather than efficiency.

This reliance imposes series limits, with engineers often needing to design around backward compatibility, which restricts architectural innovation and adds latency, bottlenecks, and power overhead. For AI and other high-performance computing workloads, these constraints directly impact performance, preventing hardware from fully exploiting parallelism or the potential of modern silicon. In short, the evolution of interconnects solved past problems but now acts as a ceiling on what engineers can achieve with today’s demanding workloads.

Huawei’s UB-Mesh: A Unified Approach to Data Center Interconnects

In response to the growing need for new connectivity options that can meet the demands of modern computing, Huawei has recently introduced UB-Mesh, a unified interconnect protocol designed to replace the patchwork of PCIe, CXL, NVLink, and TCP/IP within AI data centers. The goal is ambitious: a single protocol capable of connecting CPUs, GPUs, NPUs, memory, SSDs, NICs, and switches across both intra- and inter-rack environments. By doing so, Huawei aims to reduce latency, lower costs, and improve reliability in gigawatt-class AI deployments. Notably, the company plans to open-source the protocol, inviting broader adoption and collaboration.

Independent analysis of UB-Mesh, presented at Hot Chips 2025, positioned the protocol as a direct response to scalability challenges in AI supernodes. Huawei emphasised that current interconnects, including PCIe and Ethernet, struggle to sustain bandwidth as clusters scale to tens of thousands of accelerators. The UB-Mesh fabric is intended to unify memory addressing and inter-device communication in a way that simplifies orchestration across these vast systems.

SuperNode Vision and Performance Claims

The UB-Mesh approach reimagines the data center as a coherent “SuperNode,” unifying up to a million processors with pooled memory and storage. Huawei claims per-chip bandwidth ranging from 100 Gbps to 10 Tbps, with hop latencies reduced to roughly 150 ns, well beyond what PCIe 8.0 or conventional Ethernet can provide. By shifting from asynchronous DMA to synchronous load/store semantics, the architecture aims to maximise throughput while allowing high-speed SERDES connections to be flexibly reused.

Technical details outlined in the arXiv preprint show that UB-Mesh introduces a global address space to support coherent memory access across heterogeneous devices. This approach aligns with trends in HPC and AI workloads, where the ability to pool and dynamically allocate resources is becoming essential for efficiency.

While the design introduces a number of challenges, Huawei have proposed a number of solutions to mitigate such issues. Typically, such scaling across a data center requires a mix of copper and optical links, and optical connections inherently suffer higher error rates. However, Huawei addresses this with link-level retries, redundant lanes, and cross-module connectivity to maintain availability. Furthermore, reliability is further enhanced at the system level, with hot-spare racks automatically taking over for failed units, extending mean time between failures, a critical consideration in million-chip systems.

Balancing Reliability and System Efficiency

An important distinction raised during Huawei’s presentation is the balance between resilience and efficiency. For example, UB-Mesh employs link-level retry mechanisms that reduce the need for over-provisioning bandwidth, yet still maintain system-level fault tolerance. Such design trade-offs reflect the protocol’s ambition to be both cost-effective and technically robust, an aspect often scrutinised in hyperscale AI deployments.

Large clustered systems also introduce a significant cost factor. Conventional interconnects scale linearly with node count, which can make networking more expensive than the compute hardware itself. UB-Mesh, however, is designed to scale sub-linearly, adding capacity without proportionally increasing cost. Early demonstrations, such as an 8,192-node hybrid CLOS and 2D mesh system, have at least shown that the concept is technically feasible.

Scaling Economics of AI Interconnects

Scaling economics remain central to UB-Mesh’s value proposition. Huawei’s technical documentation suggests that as clusters expand, the fabric introduces sub-linear cost growth by reducing redundant routing overheads. This contrasts with Ethernet-based networks, where cost typically scales linearly with node count due to increased switch complexity.

But strategically, UB-Mesh represents a significant push by Huawei to reduce dependence on Western interconnect standards and establish a vertically integrated AI data center ecosystem. Whether the protocol and SuperNode architecture gain traction beyond Huawei’s own deployments remains uncertain, but adoption will depend on the willingness of third-party data center operators to consolidate infrastructure around a single vendor. Competing standards, including NVLink, UALink, and Ultra Ethernet, remain entrenched, supported by multiple suppliers, and flexible enough to accommodate a range of deployment models.

Industry observers note that while UB-Mesh positions itself as a disruptive alternative, its adoption will depend on interoperability with existing software stacks and middleware. According to technical commentary, many AI frameworks have been optimised around PCIe and Ethernet assumptions, meaning migration to UB-Mesh may require significant adaptation in system software and developer tools.

Could This New Concept from China Become the Norm?

China’s UB-Mesh initiative is deliberately being open-sourced, signalling an attempt to influence industry standards rather than simply deploy proprietary infrastructure. By making the protocol freely available, Huawei is likely trying to encourage adoption and build momentum around a unified interconnect framework.

Whether UB-Mesh is objectively superior is still open to debate. Early technical claims are impressive, but the architecture must prove itself under large-scale deployment and across diverse workloads. If successful, however, it could fundamentally change computation. A unified device map would allow CPUs, GPUs, memory, and accelerators to communicate efficiently, enabling rapid data movement and massive scalar or vector operations without relying on traditional networked switches and bridges.

Overall, UB-Mesh has the potential to reset the baseline for data center interconnects. Its adoption could mark the start of a new era in high-performance computing, one where design constraints imposed by decades of legacy standards are finally removed, giving engineers freedom to optimise both hardware and software for AI-scale workloads.