Breakthrough unlocks foundational AI platform IP on nanosheet processes

Alphawave Semi has successfully taped out of one of the industry's first UCIe IP subsystem on TSMC's N2 process, supporting 36G die-to-die data rates. The solution is fully integrated with TSMC's Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology, unlocking breakthrough bandwidth density and scalability for next-generation chiplet architectures.

This milestone builds on the recent release of the the company's AI Platform, proving readiness to support the future of disaggregated SoCs and scale-up infrastructure for hyperscale AI and HPC workloads. With this tape-out, it becomes one of the industry's first to facilitate UCIe connectivity on 2nm nanosheet technology, marking a major step forward for the open chiplet ecosystem.

"We're proud to lead the industry into the N2 era with the first UCIe IP on this advanced node," said Mohit Gupta, senior VP and GM of Custom Silicon and IP, Alphawave Semi. "Our 36G subsystem validates a new class of high-density, power-efficient chiplet connectivity and paves the way for 64G UCIe and beyond – critical for AI and high-radix networking applications."

The company is one of the industry's first UCIe IP subsystems on TSMC's 2nm process, delivering 36G performance with 11.8Tbps/mm bandwidth density, ultra-low power and latency, and advanced features such as live per-lane health monitoring and comprehensive testability. Compliant with UCIe 2.0 standard and supporting multi protocols, including PCIe, CXL, AXI, CHI and more with its highly configurable and efficient Streaming Protocol D2D Controller.

The company is advancing key ecosystem collaborations to facilitate groundbreaking technologies, using D2D-based open chiplet interoperability to drive a broader AI connectivity platform for the industry. Its UCIe IP on the TSMC N2 process affirms its position as one of the leading enablers of scalable, open chiplet ecosystems.

"Our latest collaboration with Alphawave Semi underscores our shared commitment to driving advancements in high-performance computing through design solutions that fully leverage the performance and energy-efficiency advantages of TSMC's advanced process and packaging technologies," said Lipen Yuan, senior director of Advanced Technology Business Development at TSMC. "This milestone illustrates how close collaboration with our Open Innovation Platform (OIP) partners like Alphawave Semi can enable the quick delivery of advanced interface IP and custom silicon solutions to meet the increasing demands of AI and cloud infrastructure."