RISC-V conquers the processor market with flexibility and durability

The accessibility of RISC-V has triggered a revolution and, thanks to its open architecture, allows developers to design processors tailored to exact needs. The Fraunhofer IPMS also delivers a processor IP based on the RISC V instruction set architecture. The institute has extensive RISC-V expertise, which is employed in research projects and is actively developed.

The open-source ISA RISC-V was developed to emphasise energy efficiency and computing power for new designs. This allows small, energy-efficient and, at the same time, high-performance processors. Because the ISA is freely available, companies can design, customise, and implement RISC-V processors.

The company has also created a processor IP based on the open RISC-V ISA. The EMSA5 is a 32-bit processor with a five-stage pipeline used in embedded systems and functional safety applications such as in the automotive sector. For the latter, the IP core has an ASIL D-ready certification according to ISO 26262. The know-how of the company's development team about the RISC-V ecosystem is also utilised and further developed in research projects.