Agile Analog has released its first range of analog subsystems, including power management, PVT sensing, and sleep management. These innovative, digitally wrapped subsystems greatly decrease the effort needed to integrate multiple analog IPs into any ASIC by permitting the IP to be dropped straight into a digital design flow and connected through a standard peripheral bus, such as AMBA APB. The subsystems appear just like a normal block of digital IP with the standard interfaces that engineers can expect, making them straightforward to understand and handle. Therefore, time to market, costs and risk are hugely reduced. Initially, the company introduced three subsystems: agilePMU for power management, agilePVT - PVT sensor, and agileSMU for sleep management.
Chris Morrison, director of Product Marketing at Agile Analog, said: “I’m delighted to announce our first three subsystems. Customers are always looking for ways to reduce time to market, cost, and risk, and our new, digitally wrapped subsystems do just that. Crucially, customers no longer need to deal with the complex mixed-signal boundary between analog and digital, drastically decreasing their design effort and the risks often associated with integrating a complex array of analog IP.”
The IP blocks within a subsystem are all from the company’s existing portfolio of customisable analog IP. This enables each block within the subsystem to be customised to the customer’s precise needs while sitting within the overall digital wrapper. As with all its IP, the digitally wrapped subsystems are process and foundry-agnostic, and each design is optimised for the customer’s precise PDK. Integrating IP within a subsystem additionally improves the customer’s design by removing duplicate analog functions, decreasing design rule-checking needs, and optimising interconnects. These lead to improved noise immunity, lower power consumption and smaller area.
Another main benefit to the customer is that all the verification necessities of the analog to digital, mixed-signal, boundary are performed by the company. This greatly lowers the customer design and verification time, de-risks the design process, reduces the cost of licensing mixed-signal design tools, and streamlines integration. Customers can now add analog features to deliver product differentiation without requiring specialist analog and mixed-signal engineers and the associated costly toolchain.
The subsystems are provided with a full set of supporting collateral, including System Verilog models for straightforward integration into customers’ existing digital verification flows.