Collaboration meets a growing demand for RISC-V processor verification

03-03-2023 | Imperas Software | Industrial

Imperas Software Ltd has announced a collaboration with Synopsys, Inc to fulfil the growing demand for RISC-V processor verification. This collaboration allows mutual customers to streamline their RISC-V verification tasks using ImperasDV verification solutions and Synopsys’ VCS simulation and Verdi debug tools for enhanced efficiency to fulfil critical time-to-market and quality objectives. ImperasDV is the first commercially available verification IP for RISC-V processors, incorporating architectural validation test suites essential for RISC-V developers to provide hardware implementations that align with the expectations of the software ecosystem supporting RISC-V. It has native support for the open standard RISC-V Verification Interface and utilises a ‘lock-step-compare’ co-simulation methodology for comprehensive processor verification, including asynchronous events and debug operations.

The RISC-V open standard ISA delivers the framework for optimised processors aimed at application solutions in new and creative ways. Also, design teams can employ the new flexibility across all elements of an SoC project with implementations aimed at internal control and management functions for power, security, communications and other tasks further than the scope of a limited state machine. RISC-V is also revolutionising the HPC design space with multicore arrays, vector accelerators, and complex pipelines featuring superscalar, out-of-order, multi-issue, and hardware multithreading, to name but a few of the techniques delivered at technical conferences recently.

The new design freedoms of RISC-V are producing a growing consensus across the SoC community that RISC-V verification conditions must be integrated into SoC schedules and planning. While processor verification may not be completely new, RISC-V conveys a massive shift in verification responsibility, highlighting the need for efficient verification to accomplish key tape-out milestones and time-to-market targets. Any successful verification plan can be summarised as a high-quality stimulus to attain the coverage targets. Synopsys VCS simulation and ImperasDV offer seamless integration of testbench, processor RTL, and ImperasDV verification solutions in a combined SystemVerilog environment for ‘lock-step-compare’ co-simulation between the RTL DUT and the Imperas RISC-V processor reference model. With the close integration, the debug at the point of discrepancy can be readily explored with a friction-free transition between the Verilog RTL and the Imperas RISC-V reference model using Synopsys Verdi and the Imperas eGui.

“RISC-V adoption is growing across key market segments as SoC teams explore the flexibility of an open standard ISA for optimised processors,” said Kiran Vittal, senior director of Partner Alliances Marketing for Synopsys EDA Group. “Our collaboration with Imperas, leveraging Synopsys’ leading simulation and debug solutions, enables our mutual customers to address verification complexities for RISC-V processor cores and quickly achieve coverage convergence.”

“Simulation is the foundation supporting all of the semiconductor industry for design and verification,” said Simon Davidmann, CEO at Imperas Software Ltd. “The Imperas reference models and simulation technology are structured for close integration within co-simulation and emulation environments. With this latest collaboration with Synopsys, our mutual customers can leverage all the advantages of the ImperasDV verification solutions with the advanced innovations in Synopsys VCS high-performance simulation and Verdi debug platform for a complete SystemVerilog ‘lock-step-compare’ flow with efficient debug for RISC-V verification.”


By Seb Springall

Seb Springall is a seasoned editor at Electropages, specialising in the product news sections. With a keen eye for the latest advancements in the tech industry, Seb curates and oversees content that highlights cutting-edge technologies and market trends.