Imperas Software Ltd announces that Andes Technology Corp has certified the Imperas reference models for the complete range of Andes processor IPs with Andes Custom Extension (ACE) support and the new AndesCore N25F-SE aimed at Functional Safety applications. Developers can now use the Imperas reference models to evaluate multicore design configuration options for SoC architecture exploration, incorporating custom instructions and full design flow integration with leading EDA tool environments.
Imperas models are frequently employed in a ‘software first’ design flow that includes virtual platforms/virtual prototypes as SoC developers investigate new hardware configuration options with the application software workload and full OS supports. Conventionally, using virtual prototypes in a project for software development is a key piece of a company’s ‘shift-left’ strategy to speed up schedules. Virtual prototypes shift schedules left by months as the models are available without the delays usually associated with implementations that depend on the availability of a full RTL representation of the hardware. Now developers can also examine custom instructions with the models of the Andes cores using the ACE framework.
The ability of virtual platforms to run the same binary code as the actual hardware also has advantages for complex system analysis and functional safety applications. Functional safety applications require a high system and software quality standard, which has implications for project planning, tools and methodology. Functional safety is not merely about fixing conventional software bugs and errors but also subjecting the whole platform to unprecedented situations and functional stress conditions. This may involve complex combinations of external factors and internal operational modes of the device. Virtual platforms support the analysis phase with control and visibility and deliver automation with integration into systems for CI/CD. In functional safety applications, scenarios, including internal system failures and cascading event priorities, can be simulated utilising virtual platforms with ease and repeatability to stress test the system that may be hard or even impracticable to accomplish with physical prototypes.
“RISC-V represents the potential for innovation, and it is the implementation of great ideas that are really generating exceptional results,” said Dr Charlie Su, president and CTO at Andes Technology Corp. “To unlock such potentials, Andes provides the AndeSysC environment, an extensible and near-cycle accurate SystemC model library for all AndesCore. SoC architects can use it to construct a SystemC-based virtual platform for performance evaluation of critical code segment and hardware/software co-optimisation. ACE technology helps users implement custom functions and instructions, and it directly connects to the AndeSysC environment. Now with the close integration with the Imperas fast reference models and tools, design teams can embark on architecture exploration with complete application software for the next generation of domain-specific devices with a seamless path to ACE implementation.”
“In any project, the initial inspiration phase transitions to implementation. This is mirrored in the Imperas models for Andes cores that support both the architecture exploration and integration with Andes ACE for custom instructions,” said Simon Davidmann, CEO of Imperas Software Ltd.
“Flexibility alone is insufficient for modern design flows as users depend on the established EDA tools and environments. The Imperas reference models cover the entire range of Andes cores and offer a frictionless path for users to explore the new design freedoms offered by the flexibility of RISC-V supported in all the major EDA environments.”