Imperas Software Ltd has released the first open-source SystemVerilog RISC-V processor functional coverage library for RISC-V cores. This initial release is for RV32IMC and RV64. Other ratified extensions are currently under development and will also be available as part of the riscvOVPsimPlus package with a free-to-use permissive license, which includes free commercial and academic use.
Design Verification teams employ coverage analysis as the key metric for progress toward completion of verification plans. In such a complex design as a RISC-V processor, the ISA provides the basic instruction-level functionality guidelines. Developing an instruction-level SystemVerilog functional coverage library requires an understanding of the verification process and the general requirements of the DV community. The company had previously developed these libraries over time to support numerous customer projects and users of its commercial tools, such as ImperasDV. However, with the swift growth in RISC-V adoption and many new teams currently undertaking a complex RISC-V processor DV task for the first time, the emerging RISC-V verification community urgently requires quality Verification IP from a dependable source.
Today SystemVerilog and UVM are considered the most trusted standards in SoC and IP verification.
“Functional coverage is fundamental to all modern processor verification plans; it marks the progress to project completion and release for prototype manufacture,” said Allen Baum of Esperanto Technologies, Inc., and Chair of the RISC-V International Architecture Test SIG. “The release of the Imperas SystemVerilog functional coverage library with a permissive free-to-use license will now benefit all RISC-V verification teams and complements the work of the RISC-V International Architecture Tests SIG.”
“The open standard ISA of RISC-V provides great flexibility for innovation in the design of modern processor implementations,” said Simon Davidmann, CEO at Imperas Software Ltd. “With all the configurability offered by the standard extensions and implementation options, plus users-defined custom features, the total scope of the RISC-V verification effort cannot be understated. Through our experience working with some of the most sophisticated customer designs, we recognise the usefulness of ready-to-use SystemVerilog Verification IP that allows developers a solid foundation on which to build a successful DV plan.”