Imperas Software Ltd now offers the latest RISC-V test suites and updates to the free riscvOVPsimPlus reference model, simulator and test suites. Independently developed VIP plays an essential role in any verification plan since RISC-V developers' interpretation of the specification are best tested against an independent reference. Architectural Validation test suites are essential for RISC-V to ensure hardware implementations are in line with expectations of the software ecosystem supporting RISC-V.
In May 2022, RISC-V International's Architectural Test SIG moved to use a Python program/framework v3.0 to run compliance testing and no longer offers signatures or scripts to run targets against their tests. As a service to RISC-V processor developers, Imperas has ported the RVI tests to its test framework and offers them as part of the Imperas test downloads. This means users can utilise all of the Imperas and RVI tests from one simple make/bash framework.
"With all the design freedoms that RISC-V offers, verification has never been more important to ensure full ecosystem support for new processor implementations," said Simon Davidmann, CEO at Imperas Software Ltd. "The best test for a processor is simulation-based testing to verify the interaction between the software program and the hardware operation. Architectural Validation test suites, while not a complete verification plan, offer the basic confirmation necessary to sustain the ecosystem of software support. We are pleased to offer the latest suites for the key ratified specifications of Vectors, Bit Manipulation and Crypto plus the new Embedded E suite, all for free, including commercial use, with riscvOVPsimPlus."
The technology is already in active use with many leading customers, some of which have working silicon prototypes and are now working on second generation designs. These customers, partners and users span the breadth of RISC-V adopters from open source to commercial; research to industrial; microcontrollers to high-performance computing.