Boost the dynamic performance of a broadband ADC with spur reduction IP

10-06-2022 | Teledyne FLIR | Subs & Systems

Teledyne e2v offers the EV12AQ600/5 models providing an integrated license key giving direct access to the novel ADX4 post-processing algorithm created at SP Devices within the Teledyne group of companies. The spur reduction IP dynamically attenuates spurious frequency components resulting from gain, offset and phase mismatches between the four ADC cores. Time-interleaving is a trusted architectural approach to boost ADC sampling rates. However, evading consequent spectral artefacts with calibration is particularly challenging above 10-bit resolutions and in broadband applications.

Applied to the models, time-interleaving four cores quadruples the sample rate from 1.6GS/s to 6.4GS/s. The mismatch errors between the ADC cores lower spurious free performance. ADX4 produces a spurious-free dynamic range boost of up to 10dB. That boost is particularly noticeable in broadband applications, and as it needs no hardware design changes is provided on demand. The ADX4 code module is just programmed into the post-processing FPGA. A modification that can even be retrofitted in the field.

It could not be easier to gain ADX4 dynamic enhancements. Through the desired supply chain, customers need just transition their orders over to the -ADX4 options of their device. Furthermore, they need to add the module to their Xilinx FPGA code load.

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