Imperas Software Ltd has released the ImperasDV as the integrated solution for RISC-V processor verification. The innovation and impact of RISC-V on the design side is pushing new developments over all segments and applications of the semiconductor market. Now, with this solution, SoC developers have a reliable, reference model-based solution for verification that is compatible with the existing UVM SystemVerilog methods for SoC verification.
Due to the expansive range of configuration possibilities within the RISC-V specifications, the verification task has previously needed extensive set-up and time-consuming manual adjustments to the established SoC design and verification flow. This is particularly the case when custom extensions or modifications are incorporated during the design, which are often iterated with the common HW/SW co-design as the software-driven design style examines additional custom feature optimisations. The increasing popularity of open-source IP also adds to the growth in teams undertaking verification as an in-coming quality inspection which is part of initial phase of an SoC project. Also, the design option to modify or extend the base core functionality will depend on a working DV framework from the start.
ImperasDV is designed as a solution for easy, high-quality processor verification adoption within the established SoC DV flows based on UVM and SystemVerilog. The key components include Imperas RISC-V golden reference model, integrated test bench components, test suites, and professional support and training.