Microchip Technology now makes it possible to realise 5G performance with the first single-chip, highly integrated, low-power, multi-channel IC coupled with the company’s IEEE 1588 PTP and clock recovery algorithm software modules.
“Our newest ZL3073x/63x/64x network synchronisation platform implements sophisticated measure, calibrate and tune capabilities, thereby significantly reducing network equipment time error to meet the most stringent 5G requirements,” said Rami Kanama, vice president of Microchip’s timing and communications business unit. “A uniquely flexible architecture for implementing the necessary channel density as well as high-performance, low-jitter synthesisers help simplify the design of timing cards, line cards, Radio Units (RU), Centralized Units (CUs) and Distributed Units (DUs) for 5G Radio Access Networks (RAN).”
The company's measure, calibrate and tune capabilities assure 5G systems deliver ITU-T Standard G.8273.2 Class C (30ns max|TE|) and the emerging Class D (5ns max|TEL|) time error requirements. The architecture offers flexibility, providing up to five independent DPLL channels while consuming only 0.9W of power in a compact 9mm x 9mm package that simultaneously lessens board space, power and system complexity.
With five ultra-low-jitter synthesisers, this latest platform provides 100fs RMS jitter performance needed by high-speed interfaces in the latest 5G RU, DU and CU systems.
The company's network synchronisation platform software incorporates its ZLS30730 high-performance algorithm together with its ZLS30390 IEEE 1588-2008 protocol engine. Both are widely deployed in 3G, 4G and 5G networks with precise timing capabilities.
This network synchronisation platform combines seamlessly with the company’s family of precision 5G oscillators. Its extensive portfolio of timing and clock solutions include clock generation, fanout buffer and jitter attenuator solutions, as well as quartz and MEMS oscillators, is complemented by a wide family of Ethernet PHY devices.