Cadence Design Systems announced the Cadence IP for GDDR6 is silicon-proven on TSMC’s N6, immediately obtainable on both N6 and N7 and forthcoming for TSMC N5 process technologies. The GDDR6 IP comprises Cadence PHY and controller Design IP and Verification IP that is aimed at very high-bandwidth memory applications including automotive, hyperscale computing, 5G communications and consumer, with special relevance to the memory interface in AI/ML chips. Using the technologies, customers can develop chips that connect to GDDR6 memory quicker and with lower risk.
“The combination of Cadence’s Design IP for GDDR6 and TSMC’s N6 process enables silicon designs for AI/ML, hyperscale and other computationally intense applications,” said Suk Lee, senior director of Design Infrastructure Management Division at TSMC. “We look forward to a continued partnership with Cadence to help our customers achieve high performance with design solutions, benefiting from the significant performance and power improvements of TSMC’s advanced process technologies.”
“The Cadence Design IP for GDDR6 on TSMC’s N6 and N7 processes is immediately available,” said Sanjive Agarwala, corporate vice president, R&D in the IP Group at Cadence. “Our latest PHY and controller Design IP for GDDR6 now provides DRAM data rates at 16Gbps on the TSMC N6 and N7 processes, marking it as the first in the family of devices in advanced TSMC nodes. Additionally, we have taped out GDDR6 on the TSMC N5 process.”
“Micron’s GDDR6 memory is rapidly gaining traction beyond graphics and into emerging areas such as AI/ML, networking and professional visualisation, all of which demand high-bandwidth solutions,” said Malcolm Humphrey, vice president and general manager of the core compute business for the Compute and Networking Business Unit at Micron. “Together, the Cadence IP featured in the latest TSMC N6 and N7 process technologies and Micron’s GDDR6 memory are accelerating the industry’s next generation of memory-intensive compute solutions.”