Serial memory controller for high-performance data centre computing

07-08-2019 | Microchip Technology | Semiconductors

Microchip Technology has announced an expanded data centre portfolio and its entrance into the memory infrastructure market with what is claimed to be the industry’s first commercially available serial memory controller. The SMC 1000 8x25G allows CPUs and other compute-centric SoCs to employ four times the memory channels of parallel attached DDR4 DRAM within the same package footprint. The company's serial memory controllers achieve higher memory bandwidth and media independence to these compute-intensive platforms with ultra-low latency.

The SMC 1000 8x25G interfaces to the CPU via 8-bit OMI-compliant 25Gbps lanes and bridges to memory via a 72-bit DDR4 3200 interface. The result is a significant reduction in the needed number of host CPU or SoC pins per DDR4 memory channel, providing for more memory channels and improving the memory bandwidth available.

A CPU or SoC with OMI support can use a wide set of media types with varying cost, power and performance metrics without needing to integrate a unique memory controller for every type. In contrast, CPU and SoC memory interfaces today are generally locked to specific DDR interface protocols, such as DDR4, at specific interface rates. The SMC 1000 8x25G is the first memory infrastructure product in the company's portfolio that allows the media-independent OMI interface.

“Microchip is excited to introduce the industry’s first serial memory controller device to the market,” said Pete Hazen, vice president of Microchip’s Data Centre Solutions business unit. “New memory interface technologies such as Open Memory Interface enable a broad range of SoC applications to support the increasing memory requirements of high-performance data centre applications. Microchip’s entrance into the memory infrastructure market underscores our commitment to improving performance and efficiency in the data centre.”

“IBM customer workload requirements are increasingly memory-intensive, which is why we have made the strategic decision for POWER processor memory interfaces to utilize OMI standard interfaces to increase memory bandwidth,” said Steve Fields, chief architect of IBM Power Systems. “IBM appreciates the partnership with Microchip to deliver this solution.”

By Natasha Shek