Differential clock buffers meet demand for higher design margin in terabit communications

08-07-2019 | Diodes Inc | Semiconductors

Diodes Incorporated has launched the PI6C59xxxxx series of differential clock buffers. The series provides Ethernet speeds up to 400Gbit/s and is ideal for high-performance applications including data centres and 5G base stations.


The series of differential clock buffers offers better signal margin while extending the drive ability of all clock and data signals utilised in high-speed communications. It covers a broad number of speeds and technologies, as well as combinations of input and output configurations.


The devices in the series have been created to improve the fanout of clock sources and increase clock and data distribution in communication applications working between 1.5GHz and 6GHz. This covers 25G, 40G, 56G, 100G, and 400GbE, as necessitated by a broad mixture of applications where low jitter and fast rise/fall times are needed. The ultra-low additive jitter of the devices is around 10fs, to achieve improved jitter margins to keep overall accuracy. All devices are offered in the TQFN package outline and give good thermal conductivity in a small footprint. This is increasingly important for data centre and base station applications, where suppliers need increased performance, bandwidth, power density, and functionality.


With 13 variants in the series, it embraces all of the main signalling technologies employed in high-speed networking, including CML, LVDS, LVPECL and SSTL, as well as LVCMOS. Configurations include 2, 4, 12, and 16-output for fanout buffers and data/clock buffers.

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