X-FAB Silicon Foundries, together with crowd-sourcing IC platform partner Efabless Corporation, launched the first-silicon availability of the Efabless RISC-V SoC reference design. This open-source semiconductor project went from start of design to tape-out in less than three months employing the Efabless design flow produced on open-source tools. The mixed-signal SoC, called Raven, is based on the community developed ultra-low power PicoRV32 RISC-V core. Efabless has bench-tested the Raven at 100MHz, and based on simulations, the solution should operate at up to 150MHz.
Raven is unique in that the open-source top-level design utilises X-FAB proprietary analog IP and is created with an open-source design flow. This hybrid open-source design brings the power of open innovation and at the same time protecting the significant investment in proprietary IP.
"The successful partnership with Efabless demonstrates X-FAB’s continued commitment to open-source semiconductor development", said Ulrich Bretthauer, product marketing manager at X-FAB. "Nearly 75% of Raven's die area is covered by X-FAB standard library blocks and macros. Using these proven IP blocks increased the reliability of the Raven while minimising first-silicon risk."
According to Mohamed Kassem, Efabless co-founder and CTO, "This project would not have been possible without the support of X-FAB. They have been an early adopter of the Efabless open-innovation model and this project is the logical extension of our collaboration.”