PLL synthesizer can simplify system architecture and reduce cost

25-03-2019 | Analog Devices | Semiconductors

Analog Devices ADF41513 PLL Synthesizer is an ultra-low-noise frequency synthesizer that can be used to implement Local Oscillators as high as 26.5GHz in the upconversion and downconversion sections of wireless receivers and transmitters. When utilised with an external loop filter and VCO, the device can implement a completed Phase-Locked Loop. The wide 1GHz to 26.5GHz bandwidth of the device removes the requirement for a frequency doubler or divider stage, simplifying system architecture and reducing cost.

The device is created on a high-performance SiGe, BiCMOS process, obtaining a normalised phase noise floor of -235dBc/Hz. The PFD runs up to 250MHz (integer-N mode)/125MHz (fractional-N mode) for improved phase noise and spur performance. The variable modulus, ?-? modulator enables remarkably fine resolution when using a 49-bit divide value. The device can be used as an integer-N PLL or can be employed as a fractional-N PLL with either a fixed modulus for subhertz frequency resolution or variable modulus for subhertz exact frequency resolution.

The PLL Synthesizer is provided in a compact, 24-lead, 4mm x 4mm LFCSP, perfect for space constrained applications.

Related product news