Logic analysers offers large data buffer, built-in bus receivers for serial decoding

03-01-2019 | Saelig | Test & Measurement

Saelig Company has introduced the Ikalogic SP2 Series of compact 9-channel 200MHz Logic Analysers, offering in-depth analysis of logic signals and protocol decoding with 200MHz (5ns) timing resolution. The nine channel design allows 8-bit parallel data to be captured along with a clock or strobe signal at the maximum sampling rate without any trade-off within the number of active channels and the sampling rate. This is achieved due to an embedded 2Gb memory that buffers the captured signals before sending to an attached PC. Powerful trigger options are offered which include logic change on one or various channels, trigger on timed logic signals sequence, edge trigger, trigger on protocol word or event.

The series makes it simple to analyse CMOS logic signals and industrial buses. The series comprises two devices: the SP209 is the standard edition, and the SP209i is an industrial version with specialised receivers for most common industrial busses like RS485, RS232 or CAN. The Trigger-in and Trigger-out SMA connectors enable users to synchronise the SP209 to other lab equipment, developing highly sophisticated test setups. The Spartan 6 FPGA design gives the processing power needed and can readily be firmware-updated.

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