Next-generation cloud datacenter infrastructure delivers industry-leading PPA efficiency
Cadence Design Systems has unveiled what is claimed to be the industry’s first silicon-proven, long-reach 112G SerDes IP in 7nm. The Cadence 7nm 112G PAM-4 SerDes IP produces industry-leading power, performance and area (PPA) efficiency needed to build high-port density networking products for next-generation cloud-scale and telco datacenters. The company has been working closely with early adopter clients, who have shown strong interest in this innovative technology.
Increasing mobile data consumption, burgeoning AI and machine learning applications, and emerging 5G communications needs demand ever-increasing bandwidth, stretching the existing cloud datacenter server, storage and networking infrastructure. Early adopters in the high-end cloud datacenter market are now introducing 400G Ethernet ports, with 400G Ethernet anticipated going mainstream in 2020 as early adopters begin 800G Ethernet deployment. 112G SerDes technology doubles the data rate of 56G SerDes, satisfying the exploding high-speed connectivity requirements for emerging data-intensive applications such as machine learning and neural networks.
“The 112G SerDes is a new and critical enabling technology that allows the industry to build out the next-generation 100G, 400G and 800G Ethernet cloud infrastructure more rapidly and cost-effectively,” said Lip-Bu Tan, chief executive officer of Cadence. “Our silicon-proven 112G long-reach multi-rate SerDes IP places Cadence at the forefront of high-performance computing system design enablement. By enabling 100Gb/sec per lane, Cadence’s solution reduces the lane count, heat dissipation and cost required to build the next generation of hyperscale infrastructure.”