23-08-2021 | By Robin Mitchell
Recently, Intel announced the next generation of FET technology, the RibbonFET, and how it will power their future devices. How has transistor technology changed, what is RibbonFET, and when will devices be produced using it?
Transistors have undergone many design changes since the development of the world’s first point-contact transistor in 1947. Each change in design enabled transistors to cope with new environments, improve their performance, and help new technologies. For example, the introduction of the BJT allowed the creation of high-speed logic circuits (TTL), while the introduction of the MOSFET enabled high-input impedance designs.
Of all-transistor technologies, MOSFETs have enabled some of the most significant advancements thanks to their ability to operate at high speeds, require virtually no current to function and be easily used in complementary circuits. Even though the concept of using insulation layers between a gate and channel has not changed, the method in which this is achieved has.
The first MOSFETs were planar in design, with a gate layer being separated over a channel using an insulation barrier. This design was eventually modified to produce FinFET, whereby the transistor channel is raised to create fins while the gate surrounds the fin. This provides FinFETs with better control over the current through the channel, thereby enabling lower voltages and higher frequencies. The FinFET concept was then taken further with FinFET transistors that use multiple gates to provide better control over the channel.
Recently, Intel announced the development of a new transistor technology called RibbonFET. The idea behind FinFET is to try and surround the channel with the gate as much as possible. However, FinFET cannot allow the channel to be entirely separated as the channel material is a part of the underlying semiconductor substrate (which is what the wafer is made from).
However, a RibbonFET device raises the channel off the base material, creating channel wires that enter a block of gate material. Since the channel wires are shaped like ribbons, the new FET technology is called RibbonFET, and the gate surrounds the channel completely. This unique design significantly improves the electrostatic properties of the transistor as well as reduces the size of the transistors for the same node technology.
But this is not the only technological improvement Intel has made; they have developed a new power routing technology called PowerVia. Traditional semiconductors have a planer piece of semiconductor that forms transistors, and then wire layers are added to provide power and signals. Mixing power and signals creates routing challenges and reduces the overall efficiency of the resulting device.
To overcome this, Intel has announced PowerVia that moves the power connections to transistors to the underside of the wafer. Simply put, the introduction of PowerVia is the equivalent of when PCBs moved from one-sided to double-sided layers. Suddenly, power and signal wires can be separated, making both layers far more efficient. Intel will be using both new processes by 2024 and will have a node size of 2nm.
The development of RibbonFET demonstrates how semiconductor manufacturers are starting to move away from traditional design methods. 2D planar semiconductor wafers have been more than sufficient since the invention of the first microchips as transistors could continually be shrunk in size. Now that transistor shrinking is a challenge, researchers have to develop other techniques to increase transistor count.
Using a channel that is entirely separated from the underlying semiconductor materials means that researchers could, in theory, create multiple transistor layers on a chip. If this stacking of transistors can be achieved commercially, the electronics industry will enter a new revolution in chip design.