07-12-2017 | | By Paul Whytock
Developing 5nm chip designs has been on the minds of major semiconductors companies for years. Electronics designers have dreamed and schemed about a technology that will undoubtedly offer serious improvements in power efficiency and device performance.
In direct comparison to the engineering enthusiasm regarding 5nm, those fiscally cautious corporate bean counters have sat worrying about where the money is coming from, not only in terms of developing the technology but manufacturing it. Admittedly, neither of these comes cheap with 5nm.
However, breakthroughs have occurred that predictably mean that, despite the money men's inherent frugality, 5nm is a reality and in the longer-term the costs of mass production will be reduced and the required economies of scale achieved. IBM is a prime example. Big Blue in partnership with Samsung and GlobalFoundries developed a process for building 5nm devices. It involves the use of gate-all-around transistors (GAAFETs) with the gate material being wrapped around three horizontal silicon nanosheets. This is in direct contrast to the vertical FinFET configuration..
IBM is, to say the least, bullish about 5nm device operating advantages and says chips based on that process could achieve as much as 40% performance improvements when stacked up against existing 10nm devices. And that's by using the same amount of power. Regarding the question of device power consumption, the company believes savings of up to 75% may be possible.
However, don't expect to see 5nm devices in quantity any time soon. Monetising the technology will take a few years but meantime more developments are emerging that will ensure widespread adoption of 5nm will happen.
One interesting example comes from nanotechnology centre Imec when it recently demonstrated vertically stacked gate-all-around (GAA) silicon nanowire transistors. An enhanced CMOS process was employed to integrate the transistors in a ring oscillator. This says Imec is a technology that will help make 5nm a reality.
There is no doubt that gate-all-around (GAA) MOSFETs on vertically stacked horizontal nanowires could supersede FinFETs in sub-5nm technology nodes. This would of course push current CMOS technology beyond its scaling limits. This innovative transistor architecture offers a more aggressive gate pitch scaling than FinFETs because it provides improved electrostatic control. Also, in standard cells where only one fin device is allowed, nanosheets provide more current per footprint than fins and can drive higher capacitive loads.
However, such architectural innovation requires new thinking regarding processing and a joint development between Imec and Applied Materials has shown various alternatives for the fabrication of stacked silicon nanowire and nanosheet FETs.
One process optimisation is the implementation of a SiN Shallow Trench Isolation (STI) liners which suppresses oxidation-induced fin deformation and improves the shape control of the nanowire or nanosheet. Secondly, Selectra etch can enable nanowire/nanosheet release and inner spacer cavity formation with high selectivity and without causing silicon reflow.
So technological developments are happening that will help with 5nm technology and there are statements from fabrication companies like TSMC that production of 5nm could start in 2020.
But long term profitability given the manufacturing costs and also the steep increases in chip design costs will for the near future still be making those bean counters reach for their pocket calculators.