Pioneering next-generation UCIe-A/S chiplet interconnects for AI systems

Sarcina Technology has revealed the development of patented methodologies for the UCIe-A and UCIe-S protocols. The company's latest innovations include an optimised RDL (redistribution layer) interposer design for die-to-die interconnections, supporting data rates up to 32GT/s while optimising signal routing architecture to minimise crosstalk and maximise signal integrity.

As AI workloads continue to grow at an unprecedented pace, the semiconductor industry faces the dual challenge of performance and manufacturability. Conventional SoCs are approaching their limits in terms of size, yield and cost. The solution lies in chiplet-based architectures. The company is focused on enabling package design to achieve the system-level performance needed for next-generation AI systems.

According to Larry Zu, CEO at Sarcina Technology: "One of the key challenges we are addressing is how to arrange interconnected wires to minimise signal crosstalk and enhance signal integrity. Given the constraints in available space and manufacturing limitations – such as the number of copper layers that can be used – this is a complex problem."

Larry continues: "Extensive electromagnetic simulations confirm that Sarcina's novel interposer solutions meet stringent insertion loss and crosstalk requirements, enabling robust, high-bandwidth communication for next-generation AI accelerators and high-performance computing (HPC) systems."

The company's patented methodology for the UCIe-A protocol, using RDL interposers, delivers:

• 32GT/s die-to-die data rates fully compliant with UCIe 2.0 specifications.
• Optimised routing architecture that dramatically lowers crosstalk.
• Maximum utilisation of 3D space, with routing channels strictly confined at the die edge ('beach front') for seamless integration of UCIe-A IP.
• Multi-dimensional routing optimisations for data, clock and redundancy signals, allowing an ultra-compact 3D routing region at the beach front.
• Cost-efficient designs that minimise RDL routing layers while staying within current manufacturable limits.
• Standardised RDL layouts that enhance fabrication yield and streamline manufacturing.

The company also leads with UCIe-S interconnect methodologies, targeting organic substrates and advanced PCBs with HDI technology. These substrate-level designs achieve:

• Minimal insertion loss and crosstalk enabling long channel lengths over standard organic substrates.
• Structured multi-layer routing confined to an ultra-compact 3D space, allowing dense stacking of UCIe-S modules along the die edge without occupying external routing area.
• Compatibility with package-to-package links over organic substrates or HDI PCBs, scalable to PCIe daughter cards, acceleration modules and system baseboards.
• Verified 32GT/s performance through advanced 3D HFSS, paving the way for UCIe 3.0 adoption.
• Seamless die-to-die communication even with silicon transmitter and receiver equalisations disabled, eliminating extra transistor circuit power consumption.

By unifying UCIe-A and UCIe-S capabilities, the company provides a comprehensive design and simulation platform for chiplet interconnects across interposers, substrates and PCBs. This allows customers to:

• Partition monolithic SoCs into chiplets for higher yield and cost-efficiency.
• Integrate heterogeneous technologies (compute, memory, analogue, I/O) across process nodes.
• Incorporate silicon photonic dice and fibre array units (FAUs) with compute chiplets in a Co-Packaged Optics package, eliminating data bottlenecks that leave AI compute engines idle.
• Deploy scalable, manufacturable and high-performance solutions for AI acceleration and data-intensive computing.

Larry concludes: "At Sarcina, we are not just designing interconnects - we are helping to build the foundation of next-generation AI systems. When customers review our designs, they quickly recognise the value that Sarcina's package design brings to their AI chip. The advantages are immediately clear: enhanced performance, minimal silicon area, reduced cost, power-efficiency and ease of manufacturing. These latest innovations enable us to provide our customers with the very best package design."