New benchmark in ultra-low jitter clock buffers for high-speed connectivity

Skyworks Solutions, Inc. has released the SKY53510/80/40 family of clock fanout buffers designed to fulfil the stringent timing demands of next-generation high-speed infrastructure.

With the rollout of PCIe Gen 7 and the continued expansion of AI, cloud computing, and 5G/6G networks, timing precision has become a crucial enabler of performance. The SKY53510/80/40 family delivers a scalable, low-jitter clock buffer solution that simplifies design and improves signal integrity across a wide range of platforms. For system architects and hardware designers, this indicates faster time to market, decreased engineering overhead, and the ability to future-proof designs for emerging standards like PCIe Gen 7 and 6G wireless.

The family features a 3:1 input multiplexer (including crystal input), one single-ended output, and up to ten differential outputs. Offered in compact thermally enhanced QFN packages: 7mm x 7mm (10 outputs), 6mm x 6mm (8 outputs), and 5mm x 5mm (4 outputs), these devices are pin-compatible with industry-standard layouts for easy integration and multi-sourcing.

“Skyworks is pushing the boundaries of clock tree signal integrity,” said James Wilson, vice president and general manager of Mixed Signal Solutions at Skyworks. “Our new SKY53510/80/40 buffer family offers unmatched jitter performance and format flexibility, empowering designers to meet the demands of today’s most advanced communication and computing platforms.”

These buffers are suitable for:

• PCIe Gen 3 through Gen 7
• 56G/112G/224G SerDes
• 5G/6G mMIMO radio systems
• SyncE and broadcast video
• Medical imaging and aerospace/defence

These devices support input clock slew rates down to 0.75V/ns and output levels of 1.8V, 2.5V, and 3.3V, enabling robust PCB designs with minimal signal integrity challenges such as reflection, crosstalk, and ground bounce.

Key Features

The SKY53510/80/40 features include:

• Ultra-low additive RMS phase jitter: 35fs at 156.25MHz, 3fs at 100MHz (PCIe Gen 7)
• Universal format translation: LVPECL, LVCMOS, LVDS, HCSL, CML, SSTL, HSTL, and AC-coupled single-ended inputs; selectable LVPECL, LVDS, HCSL, or tristate outputs
• Low power operation: Separate core/output voltage supplies (1.8V, 2.5V, 3.3V)
• Integrated LDOs: >70dBc PSRR for noisy environments
• Wide temperature range: -40C to +95C ambient (-40C to +105C board)
• Low noise floor: -166 dBc/Hz for SyncE 156.25 MHz applications

The devices are ideal for pairing with the company’s Si551x Network Synchronizers, SKY63104/5/6 family of Jitter Attenuating Clocks and SKY62101 Ultra-low Jitter Clock Generators to provide complete clock tree solutions that satisfy the demanding requirements of next-generation 6G wireless infrastructure, 800G/1600G networking infrastructure, and AI data centre applications that use 112G/224 PAM4 SerDes technology.