Ultra-low jitter clock generator for data centres and communications

29-08-2023 | Skyworks | Power

The Si5360 clock generator for high-speed networking, data centre and communications equipment complements Skyworks' current market-leading Si5391/5341/5332 line of clock generators, producing higher levels of jitter performance with more clock outputs.

The clock generator combines the company's fifth-generation DSPLL and MultiSynth technologies with an ultra-low jitter VCO to deliver outstanding 55fs RMS phase jitter reference clocks for high-performance applications like 112G/224G PAM-4 SerDes and Coherent Optics that are utilised in 400G/600G/800G/1.2Tb Ethernet communications and data centre equipment.

The device is utilised in applications that demand the highest level of integration and jitter performance. All PLL components are integrated on-chip, decreasing the risk of noise coupling associated with discrete solutions and significantly simplifying the clock solution design.

The device architecture has one DSPLL with two MultiSynths, allowing the capability of generating combinations of clock output frequencies that are integer- and non-integer-related.

Suitable applications include 400/600/800G/1.2T Switches, 56G/112G/224G PAM4 SerDes clocking, Datacentre Switches/NIC/Edge Computing/Accelerator cards, Clocking for FPGAs, PHYs, memory, Clock tree generation replacing XOs, buffers, signal format translators, and test/measurement equipment.

By Seb Springall