New digital standard cell library launched

Agile Analog now offers its Digital Standard Cell Library (DSCL). It offers a comprehensive library of digital cells allowing designers to implement the digital circuits needed to control analog blocks in mixed-signal solutions. The new digital library is offered in thick-oxide-based cells, operating above the core voltage domain, minimising leakage and enabling easy migration across different process nodes, even in FINFET technologies.

Barry Paterson, Agile Analog’s CEO, explained, “The Agile DSCL has been developed to enable our customers to embed digital functionality within the analog domain. These digital cells will operate within the analog voltage domain, which avoids excessive level shifting to the core domain and enables digital control to be tightly coupled to analog IP. The DSCL has been developed to be processed agnostic and therefore is available in the same processes as our analog IP. The library fully supports industry-standard digital design methodologies by making all required views available. Our Analog Digital Cell Library is already being used successfully in customer designs to support low power, always-on solutions for applications such as IoT.”

The DSCL IP blocks may be optimised for low-power, ultra-low leakage, high density or high-speed applications. There are options for channel length and multiple track heights to provide flexibility for designers. There is a special Power Management library for specific design targets, such as low-power designs. The library can be optimised for other PPA targets to make sure that customers have the most suitable solution for their application. It is also feasible to generate models at customised PVT corners. The library offers class-leading verification and is DFM-optimised.

Traditionally, analog IP blocks need to be manually redesigned for every application and process technology, but the company has a unique way to automatically produce analog IP to precisely meet the customer’s specifications and process technology. Called Composa, it employs tried and tested analog IP circuits in the company’s Composa library. Effectively, the design-once-and-re-use-many- times model of digital IP now applies to analog IP for the first time. As the analog IP circuits in the Composa library have been extensively tested and employed in previous designs and are fully validated each time they are generated, this provides a similar level of reassurance to the digital IP world’s ‘silicon-proven’. All the major foundries are supported, including TSMC, GlobalFoundries, Samsung Foundry and SMIC, and other IC foundries and manufacturers.