Imperas Software has announced that Andes Technology has certified the Imperas reference models for the entire range of Andes IP cores with the new RISC-V P extension. Developers may now employ the Imperas reference models to evaluate multicore design configuration options for SoC architecture exploration.
The open standard RISC-V ISA has a modular structure based on multiple independent extensions that provide dedicated and enhanced functionality to optimise a processor for the destination application. The new SIMD/DSP extension, designated as ‘P’ in the specification description, supports efficient data processing applications and real-time conditions. The RISC-V International P Extension Task Group is in the closing stages of submitting the specification to the official ratification process.
The Imperas simulation technology facilitates fast and accurate virtual platforms central to modern SoC design and embedded software development. Working with lead customers, the models of the Andes cores have already been employed for commercial projects, which are now implemented in silicon.
“RISC-V is more than an ISA specification; it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations,” said Dr Charlie Su, president and CTO at Andes Technology Corp. “The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.”
“Embedded development depends on the optimised balance between hardware resources and software applications,” said Simon Davidmann, CEO at Imperas Software Ltd. “With the Imperas golden reference models, developers can explore full software development for all the Andes cores, including the new RISC-V P extension and Andes ACE custom instructions.”