Contemporary power system designs require high power density levels and small form factors to maximise system-level performance. Infineon Technologies AG tackles this challenge by concentrating on system innovation with enhancements on the component level. Adding to the 25V device introduced in February, the company now offers the OptiMOS 40V low-voltage power MOSFET. It is packaged in the Source-Down PQFN with a 3.3mm x 3.3mm2 footprint. The MOSFET mainly addresses SMPS for server, telecom, and OR-ing, as well as power tool, battery protection, and charger applications.
The SD package provides silicon that is being flipped upside down inside of the component. With that, the source potential is connected to the PCB over the thermal pad rather than the drain potential. In the end, this variant can lead to a major reduction of RDS(on) by up to 25% when compared to the current technology. The thermal resistance between junction to case (R thJC) is also greatly improved when compared to the traditional PQFN packages. The device can withstand high continuous currents of up to 194A. Further, the optimised layout possibilities and the more efficient use of the PCB provides for greater design flexibility together with the highest performance.
The MOSFET is offered in two versions, standard and Center-Gate. The Center-Gate variant is optimised for parallel operation of multiple devices.