Network synchronizer clock satisfies stringent timing demands

16-09-2020 | Mouser Electronics | Test & Measurement

Texas Instruments LMK5B12204 Network Synchronizer Clock, available from Mouser, gives jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance. These features are to satisfy the stringent timing needs of communications infrastructure and industrial applications. The ultra-low jitter and high PSNR of the device can reduce BER in high-speed serial links. The device can generate output clocks with 50fs RMS jitter using the company’s proprietary BAW VCO technology, independent of the jitter and frequency of the XO and reference inputs.

The DPLL supports programmable loop bandwidth for jitter and wander attenuation, whilst the two APLLs support fractional frequency translation for flexible clock generation. The synchronisation options supported on the DPLL incorporate hitless switching with digital holdover, phase cancellation, and DCO mode with less than 0.001ppb (part per billion) frequency step size for precision clock steering (IEEE 1588 PTP slave). The DPLL can phase-lock to a 1PPS reference input. The advanced reference input monitoring block provides robust clock fault detection and helps to minimise output clock disturbance when a loss of reference occurs.

The device can utilise a commonly available low-frequency TCXO or OCXO to set the free-run or holdover output frequency stability per synchronisation standards. Otherwise, the device can employ a standard XO when free-run or holdover frequency stability and wander are not crucial. The device is fully programmable through I2C or SPI interface and supports custom frequency configuration on power-up with the internal EEPROM or ROM. The EEPROM is factory pre-programmed and is able to be programmed in-system if required.

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