Ultra-high-speed closed-chassis analytics and debug over USB3

UltraSoC today announced a new USB solution which allows SoC and system development teams to access powerful system-level analytics, optimisation and debug abilities at speeds of 10Gbps – even in a closed chassis. The company’s USB 2.0 IP is based on a patented hardware-based bare-metal technology that needs no software running to establish communication. When combined with high-speed USB 3.1 IP from Synopsys, it enables engineers to quickly gather high volumes of rich system performance data, with access from 'cycle zero' on start-up. eUSB is also supported for access to devices created on advanced process nodes.

The silicon-proven solution is intended to be both accessible and low cost: based on USB standards there is no requirement for an expensive debug probe, it is compatible with any PC and can operate with any development tool via a simple software driver.

“The benefits of USB as a debug interface are well understood: in fact our customers have been using it in this way for many years, and tell us our solution is exceptionally robust,” said UltraSoC CEO Rupert Baines. “USB is readily accessible in products ‘off-the-shelf’ and does not require additional chip pins in order to provide high-performance access, unlike dedicated debug interfaces such as JTAG or proprietary high-speed debug ports that require a dedicated interface and an expensive debug probe. It’s, therefore, an ideal interface for accessing analytic data from electronic products which increasingly require continuous monitoring and improvement throughout their lifetime.”