KIOXIA Europe has announced that it has successfully developed its fifth-generation BiCS FLASH 3D flash memory with a 112-layer vertically stacked structure. The new device has a 512 gigabit (64 gigabytes) capacity with 3-bit-per-cell (triple-level cell, TLC) technology, for specific applications. The new device intends to fulfil ever-growing bit requirements for an extensive assortment of applications, comprising traditional mobile devices, consumer and enterprise SSDs, emerging applications enabled by the new 5G networks, AI and autonomous vehicles.
Going forward, the company will employ its new fifth-generation process technology to larger capacity devices, including 1 terabit (128 gigabytes) TLC and 1.33 terabit 4-bit-per-cell (quadruple-level cell, QLC) devices.
The company’s innovative 112-layer stacking process technology is coupled with advanced circuit and manufacturing process technology to expand cell array density by approximately 20% over the 96-layer stacking process. The new technology decreases the cost per bit and improves the manufacturability of memory capacity per silicon wafer. Furthermore, it betters interface speed by 50% and allows higher programming performance and shorter read latency.
Fifth-generation BiCS FLASH was developed together with Western Digital Corporation.