Low-jitter network synchronizer clock meets stringent timing requirements

The LMK05028 is a high-performance network synchronizer clock device, from Texas Instruments, that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The device’s low jitter and high PSNR reduce bit error rates in high-speed serial links. The device has two PLL channels and produces up to eight output clocks with 150fs RMS jitter. Each PLL domain can choose from any four reference inputs to synchronise its outputs. Each PLL channel supports programmable loop bandwidth for jitter and wander attenuation and fractional frequency translation for flexible frequency configuration. Synchronisation options maintained on each PLL channel includes digital holdover, hitless switching with phase cancellation, DCO mode with <1ppt/step for precise clock steering (IEEE 1588 PTP slave), and zero-delay mode for deterministic input-to-output phase offset. The advanced reference input monitoring block guarantees robust clock fault detection and helps to reduce output clock disturbance when a loss of reference occurs. The device can use a low-frequency TCXO/OCXO to ascertain the free-run or holdover frequency stability to sustain standards-compliant synchronisation during LOR, or a standard XO when holdover frequency stability and wander are not critical. The device is completely programmable through I2C or SPI interface and provides custom frequency configuration on power-up with the internal EEPROM or ROM. The EEPROM is factory pre-programmable and in-system programmable.